Message ID | 20231020-alvin-clk-si5351-no-pll-reset-v5-0-f0c1ba537f88@bang-olufsen.dk |
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Fri, 20 Oct 2023 04:34:24 -0700 (PDT) From: =?utf-8?q?Alvin_=C5=A0ipraga?= <alvin@pqrs.dk> Subject: [PATCH v5 0/3] clk: si5351: add option to adjust PLL without glitches Date: Fri, 20 Oct 2023 13:34:13 +0200 Message-Id: <20231020-alvin-clk-si5351-no-pll-reset-v5-0-f0c1ba537f88@bang-olufsen.dk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-B4-Tracking: v=1; b=H4sIALVlMmUC/4WPyw7CIBBFf8WwdpqBMr5W/Q/jAulUiYRWUKIx/ XdpdeHO5bnJPXfmJRJHx0nsFi8RObvk+lCAlgthzyacGFxbWChUtUSpwfjsAlh/geSoJgmhh8F 7iJz4Bmw7Y9GsiNCK4hgid+4x+/eHwmeXbn18znNZTunXjBspZa10RRtFWwL5GWqGa0xVexFTO eufwt9TsgYEU9NqjUojrtvmWP6B3t+7xGF2juP4BqsNVZQBAQAA To: Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, =?utf-8?q?Alvin_=C5=A0ipraga?= <alsi@bang-olufsen.dk> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>, Rabeeh Khoury <rabeeh@solid-run.com>, Jacob Siverskog <jacob@teenage.engineering>, Sergej Sawazki <sergej@taudac.com>, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.12.3 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); 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clk: si5351: add option to adjust PLL without glitches
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Message
Alvin Šipraga
Oct. 20, 2023, 11:34 a.m. UTC
This series intends to address a problem I had when using the Si5351A as a runtime adjustable audio bit clock. The basic issue is that the driver in its current form unconditionally resets the PLL whenever adjusting its rate. But this reset causes an unwanted ~1.4 ms LOW signal glitch in the clock output. As a remedy, a new property is added to control the reset behaviour of the PLLs more precisely. In the process I also converted the bindings to YAML. Changes: v4 -> v5: - address Rob's comments: - min/maxItems on top-level clocks: - remove unnecessary else: - remove spurious | v3 -> v4: - remove spurious | per Rob's suggestion - simplify conditional clocks/clock-names per Rob's suggestion - remove mention of clkout[0-7] still being admissible in the commit body of patch 1 - while the Linux driver still tolerates this, the new dt-bindings do not v2 -> v3: - address further comments from Rob: - drop unnecessary refs and minItems - simplify if conditions for chip variants - ignore his comment about dropping '|', as line would be >80 columns - move additionalProperties: false close to type: object - define clocks/clock-names at top-level - drop patch to dove-cubox dts per Krzysztof's comment - will send separately - collect Sebastian's Acked-by v1 -> v2: - address Rob's comments on the two dt-bindings patches - new patch to correct the clock node names in the only upstream device tree using si5351 --- Alvin Šipraga (3): dt-bindings: clock: si5351: convert to yaml dt-bindings: clock: si5351: add PLL reset mode property clk: si5351: allow PLLs to be adjusted without reset .../devicetree/bindings/clock/silabs,si5351.txt | 126 ---------- .../devicetree/bindings/clock/silabs,si5351.yaml | 265 +++++++++++++++++++++ drivers/clk/clk-si5351.c | 47 +++- include/linux/platform_data/si5351.h | 2 + 4 files changed, 311 insertions(+), 129 deletions(-) --- base-commit: f6abdcb2444f6ebe06e19cd9eee767c7c46612ae change-id: 20231014-alvin-clk-si5351-no-pll-reset-ecfac0a6550c