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[23.128.96.37]) by mx.google.com with ESMTPS id x8-20020a17090a970800b002613720fcd5si1675164pjo.35.2023.10.12.01.12.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Oct 2023 01:12:00 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id DF050806CC06; Thu, 12 Oct 2023 01:10:53 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235357AbjJLIKo convert rfc822-to-8bit (ORCPT + 19 others); Thu, 12 Oct 2023 04:10:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45742 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235358AbjJLIKi (ORCPT ); Thu, 12 Oct 2023 04:10:38 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C7A2BDB; Thu, 12 Oct 2023 01:10:32 -0700 (PDT) Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ex01.ufhost.com (Postfix) with ESMTP id 5E10724E378; Thu, 12 Oct 2023 16:10:17 +0800 (CST) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 4630C7FC9; Thu, 12 Oct 2023 16:10:17 +0800 (CST) Received: from EXMBX061.cuchost.com (172.16.6.61) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 12 Oct 2023 16:10:16 +0800 Received: from localhost.localdomain (183.27.96.95) by EXMBX061.cuchost.com (172.16.6.61) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 12 Oct 2023 16:10:15 +0800 From: Xingyu Wu To: Daniel Lezcano , Thomas Gleixner , Emil Renner Berthing , Walker Chen CC: , , "Rob Herring" , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Xingyu Wu , Samin Guo , , Conor Dooley Subject: [PATCH v6 0/3] Add timer driver for StarFive JH7110 RISC-V SoC Date: Thu, 12 Oct 2023 16:10:12 +0800 Message-ID: <20231012081015.33121-1-xingyu.wu@starfivetech.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Originating-IP: [183.27.96.95] X-ClientProxiedBy: EXCAS063.cuchost.com (172.16.6.23) To EXMBX061.cuchost.com (172.16.6.61) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Thu, 12 Oct 2023 01:10:53 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779536568214726225 X-GMAIL-MSGID: 1779536568214726225 This patch serises are to add timer driver for the StarFive JH7110 RISC-V SoC. The first patch adds documentation to describe device tree bindings. The subsequent patch adds timer driver and support JH7110 SoC. The last patch adds device node about timer in JH7110 dts. This timer has four free-running 32 bit counters and runs in 24MHz clock on StarFive JH7110 SoC. And each channel(counter) triggers an interrupt when timeout. They support one-shot mode and continuous-run mode. Changes since v5: - Rebased on 6.6-rc5. - Chnaged the number about characters of name. - Made the clkevt->periodic to a local variable. - Dropped the variables of device and base. - Used clkevt->evt.irq directly and dropped the extra copy of irq. V5: https://lore.kernel.org/all/20230907053742.250444-1-xingyu.wu@starfivetech.com/ Changes since v4: - Rebased on 6.5. - Dropped the useless enum and used value directly when writing registers. - Modified the description in Kconfig. - Add the reviewed tag in patch 3. v4: https://lore.kernel.org/all/20230814101603.166951-1-xingyu.wu@starfivetech.com/ Changes since v3: - Rebased on 6.5-rc6 - Dropped the useless enum names like 'JH7110_TIMER_CH_0'. - Dropped the platform data about JH7110 and used the register offsets directly. - Drroped the useless functions of clk_disable_unprepare(). v3: https://lore.kernel.org/all/20230627055313.252519-1-xingyu.wu@starfivetech.com/ Changes since v2: - Rebased on 6.4-rc7. - Merged the header file into the c file. - Renamed the functions from 'starfive_' to 'jh7110_' - Used function 'clocksource_register_hz' instead of 'clocksource_mmio_init'. v2: https://lore.kernel.org/all/20230320135433.144832-1-xingyu.wu@starfivetech.com/ Changes since v1: - Added description about timer and modified properties' description in dt-bindings. - Dropped the 'interrupt-names' and 'clock-frequency' in dt-bindings. - Renamed the functions and added 'starfive_' - Modified that the driver probe by platform bus. v1: https://lore.kernel.org/all/20221223094801.181315-1-xingyu.wu@starfivetech.com/ Xingyu Wu (3): dt-bindings: timer: Add timer for StarFive JH7110 SoC clocksource: Add JH7110 timer driver riscv: dts: jh7110: starfive: Add timer node .../bindings/timer/starfive,jh7110-timer.yaml | 96 +++++ MAINTAINERS | 7 + arch/riscv/boot/dts/starfive/jh7110.dtsi | 20 + drivers/clocksource/Kconfig | 11 + drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-jh7110.c | 387 ++++++++++++++++++ 6 files changed, 522 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml create mode 100644 drivers/clocksource/timer-jh7110.c