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([2a01:e0a:999:a3a0:9134:b302:d8b:a200]) by smtp.gmail.com with ESMTPSA id a4-20020a05600c224400b003fe2b081661sm18945715wmm.30.2023.10.11.04.19.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Oct 2023 04:19:13 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= <cleger@rivosinc.com> To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= <cleger@rivosinc.com>, Palmer Dabbelt <palmer@rivosinc.com>, Paul Walmsley <paul.walmsley@sifive.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Albert Ou <aou@eecs.berkeley.edu>, Jonathan Corbet <corbet@lwn.net>, Andrew Jones <ajones@ventanamicro.com>, Evan Green <evan@rivosinc.com>, Conor Dooley <conor@kernel.org> Subject: [PATCH v1 00/13] riscv: report more ISA extensions through hwprobe Date: Wed, 11 Oct 2023 13:14:25 +0200 Message-ID: <20231011111438.909552-1-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=2.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,RCVD_IN_SBL_CSS, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Wed, 11 Oct 2023 04:19:53 -0700 (PDT) X-Spam-Level: ** X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779457797113417610 X-GMAIL-MSGID: 1779457797113417610 |
Series |
riscv: report more ISA extensions through hwprobe
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Message
Clément Léger
Oct. 11, 2023, 11:14 a.m. UTC
In order to be able to gather more information about the supported ISA extensions from userspace using the hwprobe syscall, add more ISA extensions report. This series adds the following ISA extensions support: - Zfh[min] - Zvfh[min] - Zihintntl - Zvbb - Zvbc - Zvkb - Zvkg - Zvkned - Zvknh[ab] - Zvksed - Zvksh - Zvkn - Zvknc - Zvkng - Zvks - Zvksc - Zvksg - Zvkt Clément Léger (13): riscv: fatorize hwprobe ISA extension reporting riscv: add ISA extension probing for Zv* extensions riscv: hwprobe: export Zv* ISA extensions dt-bindings: riscv: add Zv* ratified crypto ISA extensions description riscv: add ISA extension probing for Zfh/Zfhmin riscv: hwprobe: export Zfh/Zfhmin ISA extensions dt-bindings: riscv: add Zfh/Zfhmin ISA extensions description riscv: add ISA extension probing for Zihintntl riscv: hwprobe: export Zhintntl ISA extension dt-bindings: riscv: add Zihintntl ISA extension description riscv: add ISA extension probing for Zvfh[min] riscv: hwprobe: export Zvfh[min] ISA extensions dt-bindings: riscv: add Zvfh[min] ISA extension description .../devicetree/bindings/riscv/extensions.yaml | 127 ++++++++++++++++++ Documentation/riscv/hwprobe.rst | 65 +++++++++ arch/riscv/include/asm/hwcap.h | 21 +++ arch/riscv/include/uapi/asm/hwprobe.h | 21 +++ arch/riscv/kernel/cpufeature.c | 21 +++ arch/riscv/kernel/sys_riscv.c | 53 ++++++-- 6 files changed, 294 insertions(+), 14 deletions(-)
Comments
On second thought, maybe it would make more sense to squash all logical commits together (dt-bindings, hwporobe, etc) with all the ISA extensions in each. Tell me if you think it would be better. Clément On 11/10/2023 13:14, Clément Léger wrote: > In order to be able to gather more information about the supported ISA > extensions from userspace using the hwprobe syscall, add more ISA extensions > report. This series adds the following ISA extensions support: > > - Zfh[min] > - Zvfh[min] > - Zihintntl > - Zvbb > - Zvbc > - Zvkb > - Zvkg > - Zvkned > - Zvknh[ab] > - Zvksed > - Zvksh > - Zvkn > - Zvknc > - Zvkng > - Zvks > - Zvksc > - Zvksg > - Zvkt > > Clément Léger (13): > riscv: fatorize hwprobe ISA extension reporting > riscv: add ISA extension probing for Zv* extensions > riscv: hwprobe: export Zv* ISA extensions > dt-bindings: riscv: add Zv* ratified crypto ISA extensions description > riscv: add ISA extension probing for Zfh/Zfhmin > riscv: hwprobe: export Zfh/Zfhmin ISA extensions > dt-bindings: riscv: add Zfh/Zfhmin ISA extensions description > riscv: add ISA extension probing for Zihintntl > riscv: hwprobe: export Zhintntl ISA extension > dt-bindings: riscv: add Zihintntl ISA extension description > riscv: add ISA extension probing for Zvfh[min] > riscv: hwprobe: export Zvfh[min] ISA extensions > dt-bindings: riscv: add Zvfh[min] ISA extension description > > .../devicetree/bindings/riscv/extensions.yaml | 127 ++++++++++++++++++ > Documentation/riscv/hwprobe.rst | 65 +++++++++ > arch/riscv/include/asm/hwcap.h | 21 +++ > arch/riscv/include/uapi/asm/hwprobe.h | 21 +++ > arch/riscv/kernel/cpufeature.c | 21 +++ > arch/riscv/kernel/sys_riscv.c | 53 ++++++-- > 6 files changed, 294 insertions(+), 14 deletions(-) >
On Thu, Oct 12, 2023 at 09:15:46AM +0200, Clément Léger wrote: > On second thought, maybe it would make more sense to squash all logical > commits together (dt-bindings, hwporobe, etc) with all the ISA > extensions in each. Tell me if you think it would be better. I don't think there's anything wrong with the current approach.
On 12/10/2023 10:21, Conor Dooley wrote: > On Thu, Oct 12, 2023 at 09:15:46AM +0200, Clément Léger wrote: >> On second thought, maybe it would make more sense to squash all logical >> commits together (dt-bindings, hwporobe, etc) with all the ISA >> extensions in each. Tell me if you think it would be better. > > I don't think there's anything wrong with the current approach. Hi Conor, Ok then, let's keep like this if there are no objection, I thought it was a bit "too many" commits just for a few lines, but at least it's unitary. Thanks Clément