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[23.128.96.38]) by mx.google.com with ESMTPS id l18-20020a656812000000b00565cc12ee24si13553155pgt.874.2023.10.10.23.51.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Oct 2023 23:51:59 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) client-ip=23.128.96.38; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=X3uhmzPg; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by fry.vger.email (Postfix) with ESMTP id 5188583EDD95; Tue, 10 Oct 2023 23:51:57 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at fry.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345857AbjJKGvp (ORCPT + 19 others); Wed, 11 Oct 2023 02:51:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51208 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345289AbjJKGvl (ORCPT ); Wed, 11 Oct 2023 02:51:41 -0400 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DE9F59E for ; Tue, 10 Oct 2023 23:51:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1697007099; x=1728543099; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=bBI2FZKsPnLrhMOSzCEEd0XdZov87F+NftJakDXO9Z4=; b=X3uhmzPg8qOpYgxiSKwifitRN+LW/YzbMzUtNxzgL4ntg/YQiPklwain 4hToW3mYvpH3Jeng/WyXKbrqZa+SbaiQoWm1qPkw/TvqlRzTY+jF7XZrj QVSs0CrMab9GweBxJS8TjCYsvxJ1XkR6koJ734Y5h7WS5Kbx9S6fz5wtM POb1r0+kRXLxjhTXf9eZueAzRrXKtlYiauMnwKxuR/8Oapaf7MF/VCBC1 DZ3YgHrn/Vz7LLHyOKIkQiwxyzBJIBuUJP2f6y6v2G4WORoamYdNFIVDb Avr8jGfnC/sMiu0RwuGwvrbGUDcMgo++JlnAF1QMQQDorS4Xalyzp3cMT g==; X-IronPort-AV: E=McAfee;i="6600,9927,10859"; a="387436946" X-IronPort-AV: E=Sophos;i="6.03,214,1694761200"; d="scan'208";a="387436946" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Oct 2023 23:51:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10859"; a="824050224" X-IronPort-AV: E=Sophos;i="6.03,214,1694761200"; d="scan'208";a="824050224" Received: from sqa-gate.sh.intel.com (HELO spr-2s5.tsp.org) ([10.239.48.212]) by fmsmga004.fm.intel.com with ESMTP; 10 Oct 2023 23:51:36 -0700 From: Tina Zhang To: Jason Gunthorpe , Kevin Tian , Lu Baolu Cc: iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Tina Zhang Subject: [v6 PATCH 0/5] Share sva domains with all devices bound to a mm Date: Wed, 11 Oct 2023 14:51:27 +0800 Message-Id: <20231011065132.102676-1-tina.zhang@intel.com> X-Mailer: git-send-email 2.39.3 MIME-Version: 1.0 X-Spam-Status: No, score=2.7 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RCVD_IN_SBL_CSS,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Tue, 10 Oct 2023 23:51:57 -0700 (PDT) X-Spam-Level: ** X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779440937609729554 X-GMAIL-MSGID: 1779440937609729554 This series is to share sva(shared virtual addressing) domains with all devices bound to one mm. Problem ------- In the current iommu core code, sva domain is allocated per IOMMU group, when device driver is binding a process address space to a device (which is handled in iommu_sva_bind_device()). If one than more device is bound to the same process address space, there must be more than one sva domain instance, with each device having one. In other words, the sva domain doesn't share between those devices bound to the same process address space, and that leads to two problems: 1) device driver has to duplicate sva domains with enqcmd, as those sva domains have the same PASID and are relevant to one virtual address space. This makes the sva domain handling complex in device drivers. 2) IOMMU driver cannot get sufficient info of the IOMMUs that have devices behind them bound to the same virtual address space, when handling mmu_notifier_ops callbacks. As a result, IOMMU IOTLB invalidation is performed per device instead of per IOMMU, and that may lead to superfluous IOTLB invalidation issue, especially in a virtualization environment where all devices may be behind one virtual IOMMU. Solution -------- This patch-set tries to fix those two problems by allowing sharing sva domains with all devices bound to a mm. To achieve this, a new structure pointer is introduced to mm to replace the old PASID field, which can keep the info of PASID as well as the corresponding shared sva domains. Besides, function iommu_sva_bind_device() is updated to ensure a new sva domain can only be allocated when the old ones cannot work for the IOMMU. With these changes, a device driver can expect one sva domain could work for per PASID instance(e.g., enqcmd PASID instance), and therefore may get rid of handling sva domain duplication. Besides, IOMMU driver (e.g., intel vt-d driver) can get sufficient info (e.g., the info of the IOMMUs having their devices bound to one virtual address space) when handling mmu_notifier_ops callbacks, to remove the redundant IOTLB invalidations. Arguably there shouldn't be more than one sva_domain with the same PASID, and in any sane configuration there should be only 1 type of IOMMU driver that needs only 1 SVA domain. However, in reality, IOMMUs on one platform may not be identical to each other. Thus, attaching a sva domain that has been successfully bound to device A behind a IOMMU A, to device B behind IOMMU B may get failed due to the difference between IOMMU A and IOMMU B. In this case, a new sva domain with the same PASID needs to be allocated to work with IOMMU B. That's why we need a list to keep sva domains of one PASID. For the platform where IOMMUs are compatible to each other, there should be one sva domain in the list. v6: - Rename iommu_sva_alloc_pasid() to iommu_alloc_mm_data(). - Hold the iommu_sva_lock before invoking iommu_alloc_mm_data(). - Remove "iommu: Introduce mm_get_pasid() helper function" patch, because SMMUv3 decides to use mm_get_enqcmd_pasid() instead and other users are using iommu_sva_get_pasid() to get the pasid value. Besides, the iommu core accesses iommu_mm_data in the critical section protected by iommu_sva_lock. So no need to add another helper to retrieve PASID atomically. v5: - Order patch "iommu/vt-d: Remove mm->pasid in intel_sva_bind_mm()" first in this series. - Update commit message of patch "iommu: Introduce mm_get_pasid() helper function" - Use smp_store_release() & READ_ONCE() in storing and loading mm's pasid value. v4: - Rebase to v6.6-rc1. v3: - Add a comment describing domain->next. - Expand explanation of why PASID isn't released in iommu_sva_unbind_device(). - Add a patch to remove mm->pasid in intel_sva_bind_mm() v2: - Add mm_get_enqcmd_pasid(). - Update commit message. v1: https://lore.kernel.org/linux-iommu/20230808074944.7825-1-tina.zhang@intel.com/ Tina Zhang (5): iommu/vt-d: Remove mm->pasid in intel_sva_bind_mm() iommu: Add mm_get_enqcmd_pasid() helper function mm: Add structure to keep sva information iommu: Support mm PASID 1:n with sva domains mm: Deprecate pasid field arch/x86/kernel/traps.c | 2 +- .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 12 +-- drivers/iommu/intel/svm.c | 14 +-- drivers/iommu/iommu-sva.c | 94 +++++++++++-------- include/linux/iommu.h | 27 +++++- include/linux/mm_types.h | 3 +- kernel/fork.c | 1 - mm/init-mm.c | 3 - 8 files changed, 93 insertions(+), 63 deletions(-)