Message ID | 20230922062834.39212-1-william.qiu@starfivetech.com |
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[23.128.96.37]) by mx.google.com with ESMTPS id d7-20020a056a0024c700b0068ffd96e1d4si3352559pfv.165.2023.09.21.23.44.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Sep 2023 23:44:20 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 50EA88371454; Thu, 21 Sep 2023 23:28:47 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229805AbjIVG2s convert rfc822-to-8bit (ORCPT <rfc822;chrisfriedt@gmail.com> + 30 others); Fri, 22 Sep 2023 02:28:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44452 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229536AbjIVG2r (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Fri, 22 Sep 2023 02:28:47 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6C64D83; Thu, 21 Sep 2023 23:28:39 -0700 (PDT) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 6983424E2B1; Fri, 22 Sep 2023 14:28:36 +0800 (CST) Received: from EXMBX168.cuchost.com (172.16.6.78) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 22 Sep 2023 14:28:36 +0800 Received: from williamqiu-virtual-machine.starfivetech.com (171.223.208.138) by EXMBX168.cuchost.com (172.16.6.78) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 22 Sep 2023 14:28:35 +0800 From: William Qiu <william.qiu@starfivetech.com> To: <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org>, <linux-mmc@vger.kernel.org> CC: Emil Renner Berthing <kernel@esmil.dk>, Rob Herring <robh+dt@kernel.org>, Jaehoon Chung <jh80.chung@samsung.com>, Ulf Hansson <ulf.hansson@linaro.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Paul Walmsley <paul.walmsley@sifive.com>, "Palmer Dabbelt" <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, William Qiu <william.qiu@starfivetech.com> Subject: [PATCH v3 0/3] Change tuning implementation Date: Fri, 22 Sep 2023 14:28:31 +0800 Message-ID: <20230922062834.39212-1-william.qiu@starfivetech.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX168.cuchost.com (172.16.6.78) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: 8BIT X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Thu, 21 Sep 2023 23:28:47 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777719114141581376 X-GMAIL-MSGID: 1777719114141581376 |
Series | Change tuning implementation | |
Message
William Qiu
Sept. 22, 2023, 6:28 a.m. UTC
Hi, This series of patches changes the tuning implementation, from the previous way of reading and writing system controller registers to reading and writing UHS_REG_EXT register, thus optimizing the tuning of obtaining delay-chain. Changes v2->v3: - Rebased to v6.6rc2. - Dropped redundant criteria. - Keeped "starfive,sysreg" in dts file. Changes v1->v2: - Rebased to v6.6rc1. - Keeped "starfive,sysreg" in dt-bindings but removed from required. - Changed the function interface name. - Maked the code implementation more concise. The patch series is based on v6.6rc2. William Qiu (3): dt-bindings: mmc: Remove properties from required mmc: starfive: Change tuning implementation riscv: dts: starfive: add assigned-clock* to limit frquency .../bindings/mmc/starfive,jh7110-mmc.yaml | 2 - .../jh7110-starfive-visionfive-2.dtsi | 4 + drivers/mmc/host/dw_mmc-starfive.c | 137 +++++------------- 3 files changed, 44 insertions(+), 99 deletions(-) -- 2.34.1
Comments
On Fri, 22 Sept 2023 at 08:28, William Qiu <william.qiu@starfivetech.com> wrote: > > Hi, > > This series of patches changes the tuning implementation, from the > previous way of reading and writing system controller registers to > reading and writing UHS_REG_EXT register, thus optimizing the tuning > of obtaining delay-chain. > > Changes v2->v3: > - Rebased to v6.6rc2. > - Dropped redundant criteria. > - Keeped "starfive,sysreg" in dts file. > > Changes v1->v2: > - Rebased to v6.6rc1. > - Keeped "starfive,sysreg" in dt-bindings but removed from required. > - Changed the function interface name. > - Maked the code implementation more concise. > > The patch series is based on v6.6rc2. > > William Qiu (3): > dt-bindings: mmc: Remove properties from required > mmc: starfive: Change tuning implementation > riscv: dts: starfive: add assigned-clock* to limit frquency > > .../bindings/mmc/starfive,jh7110-mmc.yaml | 2 - > .../jh7110-starfive-visionfive-2.dtsi | 4 + > drivers/mmc/host/dw_mmc-starfive.c | 137 +++++------------- > 3 files changed, 44 insertions(+), 99 deletions(-) > Patch 1 -> 2 applied for next, thanks! Kind regards Uffe
From: Conor Dooley <conor.dooley@microchip.com> On Fri, 22 Sep 2023 14:28:31 +0800, William Qiu wrote: > This series of patches changes the tuning implementation, from the > previous way of reading and writing system controller registers to > reading and writing UHS_REG_EXT register, thus optimizing the tuning > of obtaining delay-chain. > > Changes v2->v3: > - Rebased to v6.6rc2. > - Dropped redundant criteria. > - Keeped "starfive,sysreg" in dts file. > > [...] Applied to riscv-dt-for-next, thanks! [3/3] riscv: dts: starfive: add assigned-clock* to limit frquency https://git.kernel.org/conor/c/af571133f7ae Thanks, Conor.