From patchwork Thu Sep 21 03:36:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anshuman Khandual X-Patchwork-Id: 14335 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp5235894vqi; Thu, 21 Sep 2023 17:41:49 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG+aC4knF9cK0LBv8ejuVGldZXaOdjwN9jlhQgY4dTBsLk1WgKQueM35HbL2XcqGDFjUfk/ X-Received: by 2002:a17:903:32c7:b0:1c3:be1f:5a20 with SMTP id i7-20020a17090332c700b001c3be1f5a20mr9787280plr.23.1695343309475; Thu, 21 Sep 2023 17:41:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695343309; cv=none; d=google.com; s=arc-20160816; b=zitVvrrgbToODeNAoZs1eMumPf9A9lraxG/S/I27nJSkSywz/RHEqsjpnRXlWF1/no K0Z9IuidRfQpzj6I8YYmad9YnGPoWEMAnO2/xyrKEs1DoF1tu7iTbcfXgDbCvzmMmZmZ 2TuIphdA9mXWDlAKdKlusWtHyycTmH4ppp3zDEWoiluXb69qVVao4p/Uu25VnsAh54OF oRuDXcdtyH0urTxXNp3xwveRyQuQIb0J9Sswr/jWreaZolPyLv4FZcinbhl5jjmRYMkO pDfiT0+wwlpMyCrs+28LPSLI5RWdLpwAJPHcWPPmanR3BtFYFekVC0E6JdYOPmOTagCV maHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=o0X0IO3Jl4Kwe5uY2CWqwNQGf850Ayz9Hq3wRPGtC3U=; fh=1B1+mkCYVeZZz1DAsIIoOA2jU5pSNu/8Q01YDfzUzC8=; b=PtOSbDlOfwPq/YY1kfLSpBzxzsPEXeMFWJlA1v3wvuhPhj/X13V06tTNVECJG1B/bd tbsY/Sz77vTXC3Vd6MfaCcXwMJMbiNMyuKz957K3+PP1xtkFanKrT1QRyrSVpk1fc/rU Sp9xrQdrFRgsybbW/KkMzQy7w3a37ZvyBzlcaVV4RdZdMStOgrav4hRCWsyPaSZsKwmz gj6RDa2FNkrU3Kflrc7uUEOTa82fcSfquZ++jK/siMkmwQkLT8S28vP+HVamwo4A1iLo M3A0s5ooGwAYJ3BAx/QfTkKOOMTZiZ1Jcp86QKVD+FfvPLu+muflepKPghOtj7I24iJ3 vr7Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from morse.vger.email (morse.vger.email. [2620:137:e000::3:1]) by mx.google.com with ESMTPS id z5-20020a1709027e8500b001bc996e40cdsi2559459pla.511.2023.09.21.17.41.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Sep 2023 17:41:49 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) client-ip=2620:137:e000::3:1; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by morse.vger.email (Postfix) with ESMTP id 72D67833E1E9; Thu, 21 Sep 2023 16:01:04 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at morse.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231701AbjIUXAt (ORCPT + 29 others); Thu, 21 Sep 2023 19:00:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55366 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230198AbjIUXAg (ORCPT ); Thu, 21 Sep 2023 19:00:36 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 3217E8C63B; Thu, 21 Sep 2023 10:42:37 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 613451FB; Wed, 20 Sep 2023 20:37:17 -0700 (PDT) Received: from a077893.arm.com (unknown [10.163.32.120]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 730A73F59C; Wed, 20 Sep 2023 20:36:36 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org, suzuki.poulose@arm.com Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , Mike Leach , James Clark , Leo Yan , Jonathan Corbet , linux-doc@vger.kernel.org, coresight@lists.linaro.org, linux-kernel@vger.kernel.org Subject: [PATCH V7 0/3] coresight: etm: Make cycle count threshold user configurable Date: Thu, 21 Sep 2023 09:06:28 +0530 Message-Id: <20230921033631.1298723-1-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Thu, 21 Sep 2023 16:01:04 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777691623578357041 X-GMAIL-MSGID: 1777696305955137029 This series makes ETM TRCCCCTRL based 'cc_threshold' user configurable via the perf event attribute. But first, this implements an errata work around affecting ETM TRCIDR3.CCITMIN value on certain cpus, overriding the field. This series applies on coresight/for-next/queue. Cc: Catalin Marinas Cc: Will Deacon Cc: Suzuki K Poulose Cc: Mike Leach Cc: James Clark Cc: Leo Yan Cc: Jonathan Corbet Cc: linux-doc@vger.kernel.org Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Changes in V7: - Changed commit message for the second patch adding cc_threshold Changes in V6: https://lore.kernel.org/all/20230920095443.1126617-1-anshuman.khandual@arm.com/ - Renamed etm4_core_reads_wrong_ccitmin() as etm4_fixup_wrong_ccitmin() - Moved drvdata->ccitmin fixup inside etm4_fixup_wrong_ccitmin() Changes in V5: https://lore.kernel.org/all/20230821045216.641499-1-anshuman.khandual@arm.com/ https://lore.kernel.org/all/20230915093649.435163-1-anshuman.khandual@arm.com/ - Replaced 'where as' with single word 'whereas' - Reworked 'cc_threshold' fallback to ETM_CYC_THRESHOLD_DEFAULT Changes in V4: https://lore.kernel.org/all/20230818112051.594986-1-anshuman.khandual@arm.com/ - Fixed a typo s/rangess/ranges, - Renamed etm4_work_around_wrong_ccitmin() as etm4_core_reads_wrong_ccitmin() - Moved drvdata->ccitmin value check for 256 inside etm4_core_reads_wrong_ccitmin() - Moved the comment inside etm4_core_reads_wrong_ccitmin() Changes in V3: https://lore.kernel.org/all/20230811034600.944386-1-anshuman.khandual@arm.com/ - Added errata work around affecting TRCIDR3.CCITMIN - Split the document update into a separate patch Changes in V2: https://lore.kernel.org/all/20230808074533.380537-1-anshuman.khandual@arm.com/ - s/treshhold/threshold Changes in V1: https://lore.kernel.org/all/20230804044720.1478900-1-anshuman.khandual@arm.com/ Anshuman Khandual (3): coresight: etm: Override TRCIDR3.CCITMIN on errata affected cpus coresight: etm: Make cycle count threshold user configurable Documentation: coresight: Add cc_threshold tunable Documentation/arch/arm64/silicon-errata.rst | 10 ++++ Documentation/trace/coresight/coresight.rst | 4 ++ .../hwtracing/coresight/coresight-etm-perf.c | 2 + .../coresight/coresight-etm4x-core.c | 46 ++++++++++++++++++- 4 files changed, 60 insertions(+), 2 deletions(-)