mbox series

[V7,0/3] coresight: etm: Make cycle count threshold user configurable

Message ID 20230921033631.1298723-1-anshuman.khandual@arm.com
Headers
Series coresight: etm: Make cycle count threshold user configurable |

Message

Anshuman Khandual Sept. 21, 2023, 3:36 a.m. UTC 
  This series makes ETM TRCCCCTRL based 'cc_threshold' user configurable via
the perf event attribute. But first, this implements an errata work around
affecting ETM TRCIDR3.CCITMIN value on certain cpus, overriding the field.

This series applies on coresight/for-next/queue.

Cc: Catalin Marinas <catalin.marinas@arm.com> 
Cc: Will Deacon <will@kernel.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com> 
Cc: Mike Leach <mike.leach@linaro.org>
Cc: James Clark <james.clark@arm.com>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Jonathan Corbet <corbet@lwn.net>
Cc: linux-doc@vger.kernel.org
Cc: coresight@lists.linaro.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org

Changes in V7:

- Changed commit message for the second patch adding cc_threshold

Changes in V6:

https://lore.kernel.org/all/20230920095443.1126617-1-anshuman.khandual@arm.com/

- Renamed etm4_core_reads_wrong_ccitmin() as etm4_fixup_wrong_ccitmin()
- Moved drvdata->ccitmin fixup inside etm4_fixup_wrong_ccitmin()

Changes in V5:

https://lore.kernel.org/all/20230821045216.641499-1-anshuman.khandual@arm.com/
https://lore.kernel.org/all/20230915093649.435163-1-anshuman.khandual@arm.com/

- Replaced 'where as' with single word 'whereas'
- Reworked 'cc_threshold' fallback to ETM_CYC_THRESHOLD_DEFAULT

Changes in V4:

https://lore.kernel.org/all/20230818112051.594986-1-anshuman.khandual@arm.com/

- Fixed a typo s/rangess/ranges,
- Renamed etm4_work_around_wrong_ccitmin() as etm4_core_reads_wrong_ccitmin()
- Moved drvdata->ccitmin value check for 256 inside etm4_core_reads_wrong_ccitmin()
- Moved the comment inside etm4_core_reads_wrong_ccitmin()

Changes in V3:

https://lore.kernel.org/all/20230811034600.944386-1-anshuman.khandual@arm.com/

- Added errata work around affecting TRCIDR3.CCITMIN
- Split the document update into a separate patch

Changes in V2:

https://lore.kernel.org/all/20230808074533.380537-1-anshuman.khandual@arm.com/

- s/treshhold/threshold

Changes in V1:

https://lore.kernel.org/all/20230804044720.1478900-1-anshuman.khandual@arm.com/

Anshuman Khandual (3):
  coresight: etm: Override TRCIDR3.CCITMIN on errata affected cpus
  coresight: etm: Make cycle count threshold user configurable
  Documentation: coresight: Add cc_threshold tunable

 Documentation/arch/arm64/silicon-errata.rst   | 10 ++++
 Documentation/trace/coresight/coresight.rst   |  4 ++
 .../hwtracing/coresight/coresight-etm-perf.c  |  2 +
 .../coresight/coresight-etm4x-core.c          | 46 ++++++++++++++++++-
 4 files changed, 60 insertions(+), 2 deletions(-)

Comments

Suzuki K Poulose Oct. 16, 2023, 11:03 p.m. UTC | #1 
On Thu, 21 Sep 2023 09:06:28 +0530, Anshuman Khandual wrote:
> This series makes ETM TRCCCCTRL based 'cc_threshold' user configurable via
> the perf event attribute. But first, this implements an errata work around
> affecting ETM TRCIDR3.CCITMIN value on certain cpus, overriding the field.
> 
> This series applies on coresight/for-next/queue.
> 
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> Cc: Mike Leach <mike.leach@linaro.org>
> Cc: James Clark <james.clark@arm.com>
> Cc: Leo Yan <leo.yan@linaro.org>
> Cc: Jonathan Corbet <corbet@lwn.net>
> Cc: linux-doc@vger.kernel.org
> Cc: coresight@lists.linaro.org
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> 
> [...]

Applied, thanks!

[1/3] coresight: etm: Override TRCIDR3.CCITMIN on errata affected cpus
      https://git.kernel.org/coresight/c/0f55b43dedcd
[2/3] coresight: etm: Make cycle count threshold user configurable
      https://git.kernel.org/coresight/c/0cf805fec179
[3/3] Documentation: coresight: Add cc_threshold tunable
      https://git.kernel.org/coresight/c/2b690bebb569

Best regards,