From patchwork Tue Sep 19 10:39:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 14201 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp3283902vqi; Tue, 19 Sep 2023 03:45:26 -0700 (PDT) X-Google-Smtp-Source: AGHT+IE4xIQgpaomPlniKdbdMbdrxqRAYvce08koZXh9wsMxxFQyPCxYU6KzfR89/N8DLycYG803 X-Received: by 2002:a17:90a:a407:b0:274:4b04:392f with SMTP id y7-20020a17090aa40700b002744b04392fmr8266453pjp.24.1695120325735; Tue, 19 Sep 2023 03:45:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695120325; cv=none; d=google.com; s=arc-20160816; b=Eqd4z5TFOO51VPii7iao1OVBvoZQH1nQ3fjtCXJ0whUVyTKX+RcJ5KzSLt0aS/NqFD pt/obltvhCJB04REYiCbsOy8/phQM1yxC3mW67ZuNu/7otKo17kGjSav+smGeT3SX5qK LCBNqMCmo5q3klc9ZOweY7S9tuGzm8ixudG5v75EBPU4KgMTQkmlxXtKsLoLZxfvJZ1/ y/KrfprRPyZr1Ka+SimVRzUtd7SmcpcXlEtnvSkZ9z16L14NdAZ6qCch4PUkwCq9CZQY i13aEDSeHRtEzjwTfrHNs+acAAM2/LTHJ3p8PTmNDLCBvIdVIz/IQMB6CYT2TMSgTgUb ETJg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=DjwltteplmQVayT1x+nEaBLNiON2fmZ1Swb0AcZ5Sis=; fh=6Pv8GJxBPgLEOb7aBKvQ0v66ty4eQcOaKyfCFyguvUU=; b=ODssLLM4+kkd7CWAAmcZv4ZBNObSGJNOQCPA4j+AI0X+KaNXq1KWXmmlcuinHEK/MI pO1H7Q8AynM3LY9DPGyeHzz0g6jNT6D6WcdnB0yS/fvTA7k6DQ/Tx/IhqEjMW77ib8x2 jUmnXrBmZSzSRyknXa8E/bsjlGPAqjew/845TRG1Q9e6IVPrIJ8mQk0XsI/w6bI/9Yud 9vOy6Gr7vUFqbiQYx3DtyQdx3C6skC39SWgu3xARjozAsnuYWkpMVDdlUYnESPsWjgHJ HmhoWiNp3TLEpGEMIiutMwWHpAGHitgarMB0kgIhDcBheIK5bAuMlrV4TZXqiHORYuuy DkEw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from morse.vger.email (morse.vger.email. [2620:137:e000::3:1]) by mx.google.com with ESMTPS id oj17-20020a17090b4d9100b00274d9ad80dbsi4897357pjb.121.2023.09.19.03.45.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Sep 2023 03:45:25 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) client-ip=2620:137:e000::3:1; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by morse.vger.email (Postfix) with ESMTP id 7FA94826EDAE; Tue, 19 Sep 2023 03:39:55 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at morse.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231783AbjISKjj (ORCPT + 26 others); Tue, 19 Sep 2023 06:39:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38518 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231757AbjISKj2 (ORCPT ); Tue, 19 Sep 2023 06:39:28 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id C726E187; Tue, 19 Sep 2023 03:39:20 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A241B1FB; Tue, 19 Sep 2023 03:39:57 -0700 (PDT) Received: from donnerap.arm.com (donnerap.manchester.arm.com [10.32.101.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 52A253F67D; Tue, 19 Sep 2023 03:39:18 -0700 (PDT) From: Andre Przywara To: Lee Jones , Chen-Yu Tsai , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Icenowy Zheng , Mark Brown , Jernej Skrabec , Samuel Holland , Shengyu Qu , Martin Botka , Matthew Croughan , linux-sunxi@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 0/2] mfd: axp20x: improve support without interrupts Date: Tue, 19 Sep 2023 11:39:11 +0100 Message-Id: <20230919103913.463156-1-andre.przywara@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Tue, 19 Sep 2023 03:39:55 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777462490836252338 X-GMAIL-MSGID: 1777462490836252338 This is a more of a re-send, rebased on top of v6.6-rc2, with the tags added, and adding back the binding patch, since this seems to have fallen through the cracks somehow. Changelog below. ------------------------------ Every AXP PMIC we support sports an IRQ pin, that signals certain events to the SoC. For some of the chip's functionality an interrupt is crucial for operation (for instance a power key event), but for the basic regulator features for instance the interrupt does not add much. Recently we started seeing boards with smaller PMICs, that don't bother to connect the IRQ line to anything. So far we handled this as a special case for the AXP305, but there are more examples now that justify a more general solution. Patch 1/2 adds more PMICs to the list of chips for which the interrupts DT property is optional: this is needed to correctly describe some newer boards without the IRQ pin connected. Ideally we would make this optional for every PMIC, but it is unclear whether this is a good idea: many older the "bigger" PMICs have multiple MFD devices that require an interrupt, so not having interrupt functionality might not be feasible for their operation. Also so far all boards with those PMICs connect the IRQ pin, so there is no immediate need for such a relaxation. Patch 2/2 then generalises the "no interrupt specified" case in the MFD driver, as this was special cased for two PMIC models so far. This allows boards with an AXP313a to not specify an IRQ line: there are actually multiple boards relying on this out there. Cheers, Andre Changelog v3 ... v2: - rebased on top of v6.6-rc2 - add back binding patch - tags added Changelog v2 ... v1: - drop reordering approach, use separate cell lists instead Andre Przywara (2): dt-bindings: mfd: x-powers,axp152: make interrupt optional for more chips mfd: axp20x: Generalise handling without interrupt .../bindings/mfd/x-powers,axp152.yaml | 5 ++- drivers/mfd/axp20x.c | 44 ++++++++++--------- 2 files changed, 28 insertions(+), 21 deletions(-)