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[2620:137:e000::1:20]) by mx.google.com with ESMTP id v26-20020aa7d65a000000b005231f55294dsi1799446edr.385.2023.08.10.10.57.53; Thu, 10 Aug 2023 10:58:17 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=BFvbMmNx; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232115AbjHJRoM (ORCPT <rfc822;lanlanxiyiji@gmail.com> + 99 others); Thu, 10 Aug 2023 13:44:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52556 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233066AbjHJRoL (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Thu, 10 Aug 2023 13:44:11 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7FDD82705; Thu, 10 Aug 2023 10:44:10 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 37AHi2fT117069; Thu, 10 Aug 2023 12:44:02 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691689443; bh=78+V1xmCMlA74/IzI/mywu3u6xqRMhUuh0iKICDmXWY=; h=From:To:CC:Subject:Date; b=BFvbMmNxnc2dpmpVxHQ1vrbhRuzPSBqegAhoDziFJoLPlhqeiPNutQoQ+uyROR0QV 5bQdaoY9NtdQcx9zlz7HXsmdWLxl/Auzbdyh6aP6l3bIgzq60XcR4i22xluWT1fh9Y GDjBQ91QXtQRJ1zYV3IBUT8AKBAWOfL5y/8CiUqk= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 37AHi2SA046519 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 10 Aug 2023 12:44:02 -0500 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 10 Aug 2023 12:44:02 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 10 Aug 2023 12:44:02 -0500 Received: from uda0132425.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 37AHhxuf084260; Thu, 10 Aug 2023 12:43:59 -0500 From: Vignesh Raghavendra <vigneshr@ti.com> To: Peter Ujfalusi <peter.ujfalusi@gmail.com>, Vinod Koul <vkoul@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org> CC: <dmaengine@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, Vignesh Raghavendra <vigneshr@ti.com>, <linux-arm-kernel@lists.infradead.org> Subject: [PATCH 0/3] dt-bindings: dma: ti: k3* : Update optional reg regions Date: Thu, 10 Aug 2023 23:13:52 +0530 Message-ID: <20230810174356.3322583-1-vigneshr@ti.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773865845577372647 X-GMAIL-MSGID: 1773865845577372647 |
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dt-bindings: dma: ti: k3* : Update optional reg regions
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Message
Vignesh Raghavendra
Aug. 10, 2023, 5:43 p.m. UTC
DMAs on TI K3 SoCs have channel configuration registers region which are usually hidden from Linux and configured via Device Manager Firmware APIs. But certain early SWs like bootloader which run before Device Manager is fully up would need to directly configure these registers and thus require to be in DT description. This add bindings for such configuration regions. Backward compatibility is maintained to existing DT by only mandating existing regions to be present and this new region as optional. Vignesh Raghavendra (3): dt-bindings: dma: ti: k3-bcdma: Describe cfg register regions dt-bindings: dma: ti: k3-pktdma: Describe cfg register regions dt-bindings: dma: ti: k3-udma: Describe cfg register regions .../devicetree/bindings/dma/ti/k3-bcdma.yaml | 25 +++++++++++++------ .../devicetree/bindings/dma/ti/k3-pktdma.yaml | 18 ++++++++++--- .../devicetree/bindings/dma/ti/k3-udma.yaml | 14 ++++++++--- 3 files changed, 43 insertions(+), 14 deletions(-)
Comments
On Thu, Aug 10, 2023 at 11:13:53PM +0530, Vignesh Raghavendra wrote: > Block copy DMA(BCDMA)module on K3 SoCs have ring cfg, TX and RX > channel cfg register regions which are usually configured by a Device > Management firmware. But certain entities such as bootloader (like > U-Boot) may have to access them directly. Describe this region in the > binding documentation for completeness of module description. > > Keep the binding compatible with existing DTS files by requiring first > five regions to be present at least. > > Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> > --- > .../devicetree/bindings/dma/ti/k3-bcdma.yaml | 25 +++++++++++++------ > 1 file changed, 17 insertions(+), 8 deletions(-) > > diff --git a/Documentation/devicetree/bindings/dma/ti/k3-bcdma.yaml b/Documentation/devicetree/bindings/dma/ti/k3-bcdma.yaml > index 4ca300a42a99..d166e284532b 100644 > --- a/Documentation/devicetree/bindings/dma/ti/k3-bcdma.yaml > +++ b/Documentation/devicetree/bindings/dma/ti/k3-bcdma.yaml > @@ -37,11 +37,11 @@ properties: > > reg: > minItems: 3 > - maxItems: 5 > + maxItems: 8 How come none of these reg entries have a description? What differentiates a "gcfg" from a "cfg" for example? > > reg-names: > minItems: 3 > - maxItems: 5 > + maxItems: 8 > > "#dma-cells": > const: 3 > @@ -161,14 +161,19 @@ allOf: > properties: > reg: > minItems: 5 > + maxItems: 8 > > reg-names: > + minItems: 5 > items: > - const: gcfg > - const: bchanrt > - const: rchanrt > - const: tchanrt > - const: ringrt > + - const: cfg > + - const: tchan > + - const: rchan > > required: > - ti,sci-rm-range-bchan > @@ -216,12 +221,16 @@ examples: > main_bcdma: dma-controller@485c0100 { > compatible = "ti,am64-dmss-bcdma"; > > - reg = <0x0 0x485c0100 0x0 0x100>, > - <0x0 0x4c000000 0x0 0x20000>, > - <0x0 0x4a820000 0x0 0x20000>, > - <0x0 0x4aa40000 0x0 0x20000>, > - <0x0 0x4bc00000 0x0 0x100000>; > - reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt"; > + reg = <0x00 0x485c0100 0x00 0x100>, Why have you added extra zeros? (0x00) Thanks, Conor. > + <0x00 0x4c000000 0x00 0x20000>, > + <0x00 0x4a820000 0x00 0x20000>, > + <0x00 0x4aa40000 0x00 0x20000>, > + <0x00 0x4bc00000 0x00 0x100000>, > + <0x00 0x48600000 0x00 0x8000>, > + <0x00 0x484a4000 0x00 0x2000>, > + <0x00 0x484c2000 0x00 0x2000>; > + reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt", > + "cfg", "tchan", "rchan"; > msi-parent = <&inta_main_dmss>; > #dma-cells = <3>; > > -- > 2.41.0 >
Vignesh, On 10/08/2023 20:43, Vignesh Raghavendra wrote: > DMAs on TI K3 SoCs have channel configuration registers region which are > usually hidden from Linux and configured via Device Manager Firmware > APIs. But certain early SWs like bootloader which run before Device > Manager is fully up would need to directly configure these registers and > thus require to be in DT description. > > This add bindings for such configuration regions. Backward > compatibility is maintained to existing DT by only mandating existing > regions to be present and this new region as optional. These regions were 'hidden' from Linux or other open coded access for a reason. If I recall the main reason is security and the need to make sure that the allocation of the channels not been violated. IMho the boot loader should be no exception and it should be using the DM firmware to configure the DMAs. Or has the security concern been dropped and SW can do whatever it wants? > > Vignesh Raghavendra (3): > dt-bindings: dma: ti: k3-bcdma: Describe cfg register regions > dt-bindings: dma: ti: k3-pktdma: Describe cfg register regions > dt-bindings: dma: ti: k3-udma: Describe cfg register regions > > .../devicetree/bindings/dma/ti/k3-bcdma.yaml | 25 +++++++++++++------ > .../devicetree/bindings/dma/ti/k3-pktdma.yaml | 18 ++++++++++--- > .../devicetree/bindings/dma/ti/k3-udma.yaml | 14 ++++++++--- > 3 files changed, 43 insertions(+), 14 deletions(-) >
Hi Peter, On 11/08/23 20:46, Péter Ujfalusi wrote: > Vignesh, > > On 10/08/2023 20:43, Vignesh Raghavendra wrote: >> DMAs on TI K3 SoCs have channel configuration registers region which are >> usually hidden from Linux and configured via Device Manager Firmware >> APIs. But certain early SWs like bootloader which run before Device >> Manager is fully up would need to directly configure these registers and >> thus require to be in DT description. >> >> This add bindings for such configuration regions. Backward >> compatibility is maintained to existing DT by only mandating existing >> regions to be present and this new region as optional. > > These regions were 'hidden' from Linux or other open coded access for a > reason. > If I recall the main reason is security and the need to make sure that > the allocation of the channels not been violated. > > IMho the boot loader should be no exception and it should be using the > DM firmware to configure the DMAs. > > Or has the security concern been dropped and SW can do whatever it wants? There is been a relook at the arch post this driver was upstreamed. System firmware (SYSFW) is now two separate components: TI Foundational Security (TIFS) running in a secure island and Device Management (DM) firmware (runs on boot R5 core) [0] shows boot flow diagram for AM62x. Security critical items such as PSIL pairing, channel firewalls and credential configurations are under TIFS and is handled via TI SCI calls at all times. But, things related to resource configuration (to ensure different cores dont step on each other) is under DM. Linux still needs to talk to DM for configuring these regions. But, when primary bootloader (R5 SPL) is running, there isn't a DM firmware (as it runs on the same core after R5 SPL), it would need to configure DMA resources on its own. This update is mainly to aid R5 SPL to reuse kernel DT as is. Hope that helps [0] https://u-boot.readthedocs.io/en/latest/board/ti/am62x_sk.html?highlight=am62#boot-flow (Similar boot flow for rest of K3 devices barring am65 and am64) > >> >> Vignesh Raghavendra (3): >> dt-bindings: dma: ti: k3-bcdma: Describe cfg register regions >> dt-bindings: dma: ti: k3-pktdma: Describe cfg register regions >> dt-bindings: dma: ti: k3-udma: Describe cfg register regions >> >> .../devicetree/bindings/dma/ti/k3-bcdma.yaml | 25 +++++++++++++------ >> .../devicetree/bindings/dma/ti/k3-pktdma.yaml | 18 ++++++++++--- >> .../devicetree/bindings/dma/ti/k3-udma.yaml | 14 ++++++++--- >> 3 files changed, 43 insertions(+), 14 deletions(-) >> >