mbox series

[v1,0/4] add clock controller of qca8386/qca8084

Message ID 20230809080047.19877-1-quic_luoj@quicinc.com
Headers
Series add clock controller of qca8386/qca8084 |

Message

Jie Luo Aug. 9, 2023, 8 a.m. UTC 
  qca8xxx is 4 * 2.5GBaseT ports chip, working as switch mode
named by qca8386, or working as PHY mode named by qca8084,
clock hardware reigster is accessed by MDIO bus.

This patch series add the clock controller of qca8363/qca8084,
and add the clock ops clk_branch2_qca8k_ops to avoid spin lock
used during the clock operation of qca8k clock controller where
the sleep happens when accessing clock control register by MDIO
bus.

Changes in v1:
	* remove clock flag CLK_ENABLE_MUTEX_LOCK.
	* add clock ops clk_branch2_qca8k_ops.
	* improve yaml file for fixing dtschema warnings.
	* enable clock controller driver in defconfig.

Luo Jie (4):
  clk: qcom: branch: Add clk_branch2_qca8k_ops
  dt-bindings: clock: add qca8386/qca8084 clock and reset definitions
  clk: qcom: add clock controller driver for qca8386/qca8084
  arm64: defconfig: Enable qca8k nss clock controller

 .../bindings/clock/qcom,qca8k-nsscc.yaml      |   79 +
 arch/arm64/configs/defconfig                  |    1 +
 drivers/clk/qcom/Kconfig                      |    8 +
 drivers/clk/qcom/Makefile                     |    1 +
 drivers/clk/qcom/clk-branch.c                 |    8 +
 drivers/clk/qcom/clk-branch.h                 |    2 +
 drivers/clk/qcom/nsscc-qca8k.c                | 2195 +++++++++++++++++
 include/dt-bindings/clock/qcom,qca8k-nsscc.h  |  101 +
 include/dt-bindings/reset/qcom,qca8k-nsscc.h  |   75 +
 9 files changed, 2470 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,qca8k-nsscc.yaml
 create mode 100644 drivers/clk/qcom/nsscc-qca8k.c
 create mode 100644 include/dt-bindings/clock/qcom,qca8k-nsscc.h
 create mode 100644 include/dt-bindings/reset/qcom,qca8k-nsscc.h


base-commit: 1c2c8c3517b3ba43a964afe1ff7926b13dc51492

Comments

Krzysztof Kozlowski Aug. 9, 2023, 3:32 p.m. UTC | #1 
On 09/08/2023 10:00, Luo Jie wrote:
> qca8xxx is 4 * 2.5GBaseT ports chip, working as switch mode
> named by qca8386, or working as PHY mode named by qca8084,
> clock hardware reigster is accessed by MDIO bus.
> 
> This patch series add the clock controller of qca8363/qca8084,
> and add the clock ops clk_branch2_qca8k_ops to avoid spin lock
> used during the clock operation of qca8k clock controller where
> the sleep happens when accessing clock control register by MDIO
> bus.
> 
> Changes in v1:
> 	* remove clock flag CLK_ENABLE_MUTEX_LOCK.
> 	* add clock ops clk_branch2_qca8k_ops.
> 	* improve yaml file for fixing dtschema warnings.
> 	* enable clock controller driver in defconfig.

So this is v2, not v1. Your next version, if happens, will be v3, please.

Best regards,
Krzysztof
Jie Luo Aug. 10, 2023, 4:51 a.m. UTC | #2 
On 8/9/2023 11:32 PM, Krzysztof Kozlowski wrote:
> On 09/08/2023 10:00, Luo Jie wrote:
>> qca8xxx is 4 * 2.5GBaseT ports chip, working as switch mode
>> named by qca8386, or working as PHY mode named by qca8084,
>> clock hardware reigster is accessed by MDIO bus.
>>
>> This patch series add the clock controller of qca8363/qca8084,
>> and add the clock ops clk_branch2_qca8k_ops to avoid spin lock
>> used during the clock operation of qca8k clock controller where
>> the sleep happens when accessing clock control register by MDIO
>> bus.
>>
>> Changes in v1:
>> 	* remove clock flag CLK_ENABLE_MUTEX_LOCK.
>> 	* add clock ops clk_branch2_qca8k_ops.
>> 	* improve yaml file for fixing dtschema warnings.
>> 	* enable clock controller driver in defconfig.
> 
> So this is v2, not v1. Your next version, if happens, will be v3, please.
> 
> Best regards,
> Krzysztof
> 
got it, i will use V3 in the next patch set, thanks Krzysztof.