mbox series

[v5,0/4] perf: ampere: Add support for Ampere SoC PMUs

Message ID 20230714010141.824226-1-ilkka@os.amperecomputing.com
Headers
Series perf: ampere: Add support for Ampere SoC PMUs |

Message

Ilkka Koskinen July 14, 2023, 1:01 a.m. UTC 
  Changes since v4:
    * "Support implementation specific filters" patch:
        - Added comment about filter and impdef registers and reference
          to the Coresight PMU specification to the commit message

    * "Add support for Ampere SoC PMU" patch:
	- Fixed the documentation and added more comments
        - Changed the incrementing PMU index number to idr_alloc()
	  (Needs a impdef release hook patch to release unused index)
	- Fixed style in init_ops() to more reasonable
	- Moved bank parameter to config1

Changes since v3:
    * use_64b_counter_reg => has_atomic_dword (patch 1/4)
    * Removed the unnecessary hook for group validation (patch 3/4)
    * Added group config validation to ampere_cspmu_validate_event() (patch 4/4)
    * Rebased the patchset

Changes since v2:
    * Changed to use supports_64bits_atomics() and replaced the split writes
      with lo_hi_writeq()
    * Added implementation specific group validation to patch 3
    * Dropped shared interrupt patch
    * Removed unnecessary filter_enable parameter from ampere module
    * Added group validation to ampere module

Changes since v1:
    * Rather than creating a completely new driver, implemented as a submodule
      of Arm CoreSight PMU driver
      * Fixed shared filter handling


Ilkka Koskinen (4):
  perf: arm_cspmu: Split 64-bit write to 32-bit writes
  perf: arm_cspmu: Support implementation specific filters
  perf: arm_cspmu: Support implementation specific validation
  perf: arm_cspmu: ampere_cspmu: Add support for Ampere SoC PMU

 .../admin-guide/perf/ampere_cspmu.rst         |  29 +++
 drivers/perf/arm_cspmu/Makefile               |   2 +-
 drivers/perf/arm_cspmu/ampere_cspmu.c         | 243 ++++++++++++++++++
 drivers/perf/arm_cspmu/ampere_cspmu.h         |  17 ++
 drivers/perf/arm_cspmu/arm_cspmu.c            |  29 ++-
 drivers/perf/arm_cspmu/arm_cspmu.h            |   6 +
 6 files changed, 321 insertions(+), 5 deletions(-)
 create mode 100644 Documentation/admin-guide/perf/ampere_cspmu.rst
 create mode 100644 drivers/perf/arm_cspmu/ampere_cspmu.c
 create mode 100644 drivers/perf/arm_cspmu/ampere_cspmu.h

Comments

Will Deacon July 28, 2023, 1:29 p.m. UTC | #1 
On Thu, Jul 13, 2023 at 06:01:37PM -0700, Ilkka Koskinen wrote:
> Changes since v4:
>     * "Support implementation specific filters" patch:
>         - Added comment about filter and impdef registers and reference
>           to the Coresight PMU specification to the commit message
> 
>     * "Add support for Ampere SoC PMU" patch:
> 	- Fixed the documentation and added more comments
>         - Changed the incrementing PMU index number to idr_alloc()
> 	  (Needs a impdef release hook patch to release unused index)
> 	- Fixed style in init_ops() to more reasonable
> 	- Moved bank parameter to config1

This looks pretty good to me, but I think we should merge the series
reworking the backend registration first:

  https://lore.kernel.org/all/20230705104745.52255-1-bwicaksono@nvidia.com/

and then this should slot in quite nicely. I've left a minor comment over
there and I'd like Suzuki's review, but then we're good to go.

Cheers,

Will
Ilkka Koskinen July 31, 2023, 6:56 a.m. UTC | #2 
Hi Will,

On Fri, 28 Jul 2023, Will Deacon wrote:
> On Thu, Jul 13, 2023 at 06:01:37PM -0700, Ilkka Koskinen wrote:
>> Changes since v4:
>>     * "Support implementation specific filters" patch:
>>         - Added comment about filter and impdef registers and reference
>>           to the Coresight PMU specification to the commit message
>>
>>     * "Add support for Ampere SoC PMU" patch:
>> 	- Fixed the documentation and added more comments
>>         - Changed the incrementing PMU index number to idr_alloc()
>> 	  (Needs a impdef release hook patch to release unused index)
>> 	- Fixed style in init_ops() to more reasonable
>> 	- Moved bank parameter to config1
>
> This looks pretty good to me, but I think we should merge the series
> reworking the backend registration first:
>
>  https://lore.kernel.org/all/20230705104745.52255-1-bwicaksono@nvidia.com/
>
> and then this should slot in quite nicely. I've left a minor comment over
> there and I'd like Suzuki's review, but then we're good to go.
>
> Cheers,
>
> Will

Sounds good to me. I'll try to find some time to do the needed changes to
my patches and rebase them on top of Besar's patchset.

Cheers, Ilkka