Message ID | 20230704090453.83980-1-william.qiu@starfivetech.com |
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[2620:137:e000::1:20]) by mx.google.com with ESMTP id l18-20020a17090a409200b0023def94be5esi19980954pjg.20.2023.07.04.02.25.35; Tue, 04 Jul 2023 02:25:47 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229895AbjGDJFL convert rfc822-to-8bit (ORCPT <rfc822;ybw1215001957@gmail.com> + 99 others); Tue, 4 Jul 2023 05:05:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37636 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231819AbjGDJFG (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Tue, 4 Jul 2023 05:05:06 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2EFD4E47; Tue, 4 Jul 2023 02:04:57 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id EFE328269; Tue, 4 Jul 2023 17:04:54 +0800 (CST) Received: from EXMBX068.cuchost.com (172.16.6.68) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 4 Jul 2023 17:04:55 +0800 Received: from williamqiu-virtual-machine.starfivetech.com (171.223.208.138) by EXMBX068.cuchost.com (172.16.6.68) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 4 Jul 2023 17:04:54 +0800 From: William Qiu <william.qiu@starfivetech.com> To: <devicetree@vger.kernel.org>, <linux-spi@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org> CC: Mark Brown <broonie@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Emil Renner Berthing <kernel@esmil.dk>, Ziv Xu <ziv.xu@starfivetech.com>, William Qiu <william.qiu@starfivetech.com> Subject: [PATCH v4 0/3] Add initialization of clock for StarFive JH7110 SoC Date: Tue, 4 Jul 2023 17:04:50 +0800 Message-ID: <20230704090453.83980-1-william.qiu@starfivetech.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX068.cuchost.com (172.16.6.68) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: 8BIT X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_PASS, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1770481514367449545?= X-GMAIL-MSGID: =?utf-8?q?1770481514367449545?= |
Series |
Add initialization of clock for StarFive JH7110 SoC
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Message
William Qiu
July 4, 2023, 9:04 a.m. UTC
Hi, This patchset adds initial rudimentary support for the StarFive Quad SPI controller driver. And this driver will be used in StarFive's VisionFive 2 board. In 6.4, the QSPI_AHB and QSPI_APB clocks changed from the default ON state to the default OFF state, so these clocks need to be enabled in the driver.At the same time, dts patch is added to this series. Changes v3->v4: - Added minItems for clocks. - Added clock names property. - Fixed formatting issues. Changes v2->v3: - Rebaed to v6.4rc6. - Renamed the clock names. - Changed the variable definition type. Changes v1->v2: - Renamed the clock names. - Specified a different array of clocks. - Used clk_bulk_ APIs. The patch series is based on v6.4rc6. William Qiu (3): dt-bindings: qspi: cdns,qspi-nor: Add clocks for StarFive JH7110 SoC spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoC .../bindings/spi/cdns,qspi-nor.yaml | 12 ++++++- .../jh7110-starfive-visionfive-2.dtsi | 32 +++++++++++++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 18 +++++++++++ drivers/spi/spi-cadence-quadspi.c | 20 ++++++++++++ 4 files changed, 81 insertions(+), 1 deletion(-) -- 2.34.1
Comments
On Tue, 04 Jul 2023 17:04:50 +0800, William Qiu wrote: > This patchset adds initial rudimentary support for the StarFive > Quad SPI controller driver. And this driver will be used in > StarFive's VisionFive 2 board. In 6.4, the QSPI_AHB and QSPI_APB > clocks changed from the default ON state to the default OFF state, > so these clocks need to be enabled in the driver.At the same time, > dts patch is added to this series. > > [...] Applied to https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next Thanks! [1/3] dt-bindings: qspi: cdns,qspi-nor: Add clocks for StarFive JH7110 SoC commit: 0d2b6a1b8515204924b9174ae0135e1f4ff29b21 [2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI commit: 33f1ef6d4eb6bca726608ed939c9fd94d96ceefd All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark