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[2620:137:e000::1:20]) by mx.google.com with ESMTP id bu11-20020a056a00410b00b0067dd7254cb0si11788259pfb.39.2023.07.03.03.32.01; Mon, 03 Jul 2023 03:32:14 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=gFGleEuh; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230354AbjGCK3T (ORCPT + 99 others); Mon, 3 Jul 2023 06:29:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47570 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231297AbjGCK3N (ORCPT ); Mon, 3 Jul 2023 06:29:13 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 50234C4; Mon, 3 Jul 2023 03:29:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1688380152; x=1719916152; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=9gC2ucQs56hznJJn3CZLdBAIp3rcInl7wiNCLwEz1B4=; b=gFGleEuhNogWM0mPa6vxjVkBxC29P0vpWtu5tZgTh0K1AAw4TuBNFMU6 PTunUp87HcinLGrmYIBPVhK4DcSvSUK3WfUAP4w3my4Cd4JMUi//HxXLr tj1UtYQVuwyLtWKrmfBWEnLcZksfNeaidc9zX67HlmxU1Db8+XaMbgCps 9l3ydfwwDDe91gGQbjYOv5Y5uwtaXlOSnLqDRcc4ZNuRP8qFKdGP4jjuG NBVmaQ16DWgbjrQLyUpvtUbB4pF9LdP7cQTmjdW7Rrg6nKVmLafHW5jOU v0LVz8iFjLqLjvQD1gUvdvQP+mAp/QOilYwNdt+DciFX5xe9q0mVsoYcj A==; X-IronPort-AV: E=Sophos;i="6.01,177,1684825200"; d="scan'208";a="221754598" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 03 Jul 2023 03:29:11 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 3 Jul 2023 03:28:57 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Mon, 3 Jul 2023 03:28:54 -0700 From: Conor Dooley To: CC: , , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Albert Ou , "Jonathan Corbet" , Andrew Jones , "Heiko Stuebner" , Evan Green , Sunil V L , , , , Subject: [PATCH v3 00/11] RISC-V: Probe DT extension support using riscv,isa-extensions & riscv,isa-base Date: Mon, 3 Jul 2023 11:27:52 +0100 Message-ID: <20230703-repayment-vocalist-e4f3eeac2b2a@wendy> X-Mailer: git-send-email 2.40.1 MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2944; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=9gC2ucQs56hznJJn3CZLdBAIp3rcInl7wiNCLwEz1B4=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCmLFq3c6XLDgcsgL1aUrfGD5vL/W466rspkq/9zR4tna+QZ DpOYjlIWBjEOBlkxRZbE230tUuv/uOxw7nkLM4eVCWQIAxenAExk2x1Ghu8+n1RN27+92X9uocHiE8 6tyyyy+3WtDfe0SiZzPO00KWZkmBIyVe4o6/f1bWeWsrbdyNysnzvNTX42u1DbhL2zj1Q+YQYA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1770395097646566812?= X-GMAIL-MSGID: =?utf-8?q?1770395097646566812?= Hey, Based on my latest iteration of deprecating riscv,isa [1], here's an implementation of the new properties for Linux. The first few patches, up to "RISC-V: split riscv_fill_hwcap() in 3", are all prep work that further tames some of the extension related code, on top of my already applied series that cleans up the ISA string parser. Perhaps "RISC-V: shunt isa_ext_arr to cpufeature.c" is a bit gratuitous, but I figured a bit of coalescing of extension related data structures would be a good idea. Note that riscv,isa will still be used in the absence of the new properties. Palmer suggested adding a Kconfig option to turn off the fallback for DT, which I have gone and done. It's locked behind the NONPORTABLE option for good reason. In v2, I've also come up with a more reasonable name for the new function I added & fixed up various comments from Drew and Evan. In v3, there's the new commandline option that Drew suggested. I have Also picked up a patch from Palmer that adds more helpful prints where harts fail the checks in riscv_early_of_processor_id(), and I've sprinkled a few more of those prints in my new additions to the function. Cheers, Conor. [1] https://lore.kernel.org/all/20230702-eats-scorebook-c951f170d29f@spud CC: Rob Herring CC: Krzysztof Kozlowski CC: Paul Walmsley CC: Palmer Dabbelt CC: Albert Ou CC: Jonathan Corbet CC: Andrew Jones CC: Heiko Stuebner CC: Evan Green CC: Sunil V L CC: linux-doc@vger.kernel.org CC: linux-riscv@lists.infradead.org CC: devicetree@vger.kernel.org CC: linux-kernel@vger.kernel.org Conor Dooley (9): RISC-V: drop a needless check in print_isa_ext() RISC-V: shunt isa_ext_arr to cpufeature.c RISC-V: repurpose riscv_isa_ext array in riscv_fill_hwcap() RISC-V: add missing single letter extension definitions RISC-V: add single letter extensions to riscv_isa_ext RISC-V: split riscv_fill_hwcap() in 3 RISC-V: enable extension detection from new properties RISC-V: try new extension properties in of_early_processor_hartid() RISC-V: provide Kconfig & commandline options to control parsing "riscv,isa" Heiko Stuebner (1): RISC-V: don't parse dt/acpi isa string to get rv32/rv64 Palmer Dabbelt (1): RISC-V: Provide a more helpful error message on invalid ISA strings .../admin-guide/kernel-parameters.txt | 7 + arch/riscv/Kconfig | 18 + arch/riscv/include/asm/hwcap.h | 17 +- arch/riscv/kernel/cpu.c | 177 ++---- arch/riscv/kernel/cpufeature.c | 519 ++++++++++++------ 5 files changed, 436 insertions(+), 302 deletions(-)