Message ID | 20230630142233.63585-1-amit.kumar-mahapatra@amd.com |
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Fri, 30 Jun 2023 09:22:40 -0500 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB05.amd.com (10.181.40.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Fri, 30 Jun 2023 09:22:40 -0500 Received: from xhdakumarma40u.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.23 via Frontend Transport; Fri, 30 Jun 2023 09:22:36 -0500 From: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com> To: <tudor.ambarus@linaro.org>, <pratyush@kernel.org>, <miquel.raynal@bootlin.com>, <richard@nod.at>, <vigneshr@ti.com>, <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org> CC: <git@amd.com>, <michael@walle.cc>, <linux-mtd@lists.infradead.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <amitrkcian2002@gmail.com>, Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com> Subject: [PATCH v4 0/2] mtd: spi-nor: Avoid setting SRWD bit in SR Date: Fri, 30 Jun 2023 19:52:31 +0530 Message-ID: <20230630142233.63585-1-amit.kumar-mahapatra@amd.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT053:EE_|SJ0PR12MB7457:EE_ X-MS-Office365-Filtering-Correlation-Id: 56dba14e-eb7d-4ec6-240b-08db797576f3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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mtd: spi-nor: Avoid setting SRWD bit in SR
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Message
Mahapatra, Amit Kumar
June 30, 2023, 2:22 p.m. UTC
Setting the status register write disable (SRWD) bit in the status register (SR) with WP# signal of the flash not connected or wrongly tied to GND (that includes internal pull-downs), will configure the SR permanently as read-only. To avoid this a boolean type DT property "no-wp" is introduced. If this property is defined, the spi-nor doesn't set the SRWD bit in SR while performing flash protection operation. --- BRANCH: for-next Changes in v4: - Added SNOR_F_NO_WP flag info in debugfs.c file. - Updated comments in swp.c file. - Added Reviewed-by tags in 1/2. Changes in v3: - Updated DT property name to "no-wp". - Removed Reviewed-by tag from 1/2 as the DT property name has changed. - Updated spi-nor flag name to SNOR_F_NO_WP. - Updated DT property description. - Updated patch description. - Updated comments in swp.c file. - Replaced WP with WP# in patch descriptions, comments & DT property description. Changes in v2: - Modified DT property description to add information about a valid use case. - Added Reviewed-by tag in 1/2. - Updated comment description in 2/2. --- Amit Kumar Mahapatra (2): dt-bindings: mtd: jedec, spi-nor: Add DT property to avoid setting SRWD bit in status register mtd: spi-nor: Avoid setting SRWD bit in SR if WP# signal not connected .../devicetree/bindings/mtd/jedec,spi-nor.yaml | 15 +++++++++++++++ drivers/mtd/spi-nor/core.c | 3 +++ drivers/mtd/spi-nor/core.h | 1 + drivers/mtd/spi-nor/debugfs.c | 1 + drivers/mtd/spi-nor/swp.c | 9 +++++++-- 5 files changed, 27 insertions(+), 2 deletions(-)
Comments
On Fri, 30 Jun 2023 19:52:31 +0530, Amit Kumar Mahapatra wrote: > Setting the status register write disable (SRWD) bit in the status > register (SR) with WP# signal of the flash not connected or wrongly tied to > GND (that includes internal pull-downs), will configure the SR permanently > as read-only. To avoid this a boolean type DT property "no-wp" is > introduced. If this property is defined, the spi-nor doesn't set the SRWD > bit in SR while performing flash protection operation. > > [...] Moved the of_property_read_bool() as suggested by Michael. Applied to git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git, spi-nor/next branch. Thanks! [1/2] dt-bindings: mtd: jedec, spi-nor: Add DT property to avoid setting SRWD bit in status register https://git.kernel.org/mtd/c/cfc2928cb213 [2/2] mtd: spi-nor: Avoid setting SRWD bit in SR if WP# signal not connected https://git.kernel.org/mtd/c/18d7d01a0a0e Cheers,