Message ID | 20230630120433.49529-1-prabhakar.mahadev-lad.rj@bp.renesas.com |
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Series |
Add missing pins for RZ/Five SoC
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Message
Lad, Prabhakar
June 30, 2023, 12:04 p.m. UTC
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi Geert,
This patch series intends to incorporate the absent port pins P19 to P28,
which are exclusively available on the RZ/Five SoC.
I am submitting this series as an RFC (Request for Comments) as the port
pins P19 to P28 cannot be utilized as GPIO but can be utilized as
multiplexed pins. Additionally, certain attributes such as setting the
ISEL would necessitate a device tree property to indicate ISEL. Therefore,
before proceeding with the addition of comprehensive support, I would
appreciate some input on whether an alternative approach could be considered.
Cheers,
Prabhakar
Lad Prabhakar (4):
pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK()
macro
pinctrl: renesas: pinctrl-rzg2l: Add validation of GPIO pin in
rzg2l_gpio_request()
pinctrl: renesas: pinctrl-rzg2l: Add the missing port pins P19 to P28
riscv: dts: renesas: r9a07g043f: Update gpio-ranges property
arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 4 +
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 263 +++++++++++++-------
2 files changed, 176 insertions(+), 91 deletions(-)
Comments
Hi Prabhakar, On Fri, Jun 30, 2023 at 2:04 PM Prabhakar <prabhakar.csengg@gmail.com> wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > This patch series intends to incorporate the absent port pins P19 to P28, > which are exclusively available on the RZ/Five SoC. Are you sure these are not available on RZ/G2UL? I thought RZ/Five and RZ/G2UL were identical, except for the ARM vs. RISC-V CPU core (+ support)? Gr{oetje,eeting}s, Geert