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Shenoy" , Mark Rutland , Peter Zijlstra , Marc Zyngier , =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= , Krzysztof Kozlowski Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 0/6] Add support to handle misaligned accesses in S-mode Date: Sat, 24 Jun 2023 14:20:43 +0200 Message-Id: <20230624122049.7886-1-cleger@rivosinc.com> X-Mailer: git-send-email 2.40.1 MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769588298363780538?= X-GMAIL-MSGID: =?utf-8?q?1769588298363780538?= Since commit 61cadb9 ("Provide new description of misaligned load/store behavior compatible with privileged architecture.") in the RISC-V ISA manual, it is stated that misaligned load/store might not be supported. However, the RISC-V kernel uABI describes that misaligned accesses are supported. In order to support that, this series adds support for S-mode handling of misaligned accesses, SBI call for misaligned trap delegation as well prctl support for PR_SET_UNALIGN. Handling misaligned access in kernel allows for a finer grain control of the misaligned accesses behavior, and thanks to the prctl call, can allow disabling misaligned access emulation to generate SIGBUS. User space software can then be optimized by removing such access based on SIGBUS generation. This series relies on a SBI extension [1] allowing to request delegation of the misaligned load/store traps to the S-mode software. This extension has been submitted for review to the riscv tech-prs group. This work was tested on spike since Qemu does transparently handles misaligned access. [1] https://lists.riscv.org/g/tech-prs/message/472i Clément Léger (6): riscv: remove unused functions in traps_misaligned.c riscv: add support for misaligned handling in S-mode riscv: allow S-mode to handle misaligned traps riscv: add support for SBI misalignment trap delegation riscv: add support for PR_SET_UNALIGN and PR_GET_UNALIGN riscv: add floating point insn support to misaligned access emulation arch/riscv/include/asm/processor.h | 9 + arch/riscv/include/asm/sbi.h | 12 ++ arch/riscv/kernel/Makefile | 2 +- arch/riscv/kernel/fpu.S | 118 ++++++++++++ arch/riscv/kernel/process.c | 20 ++ arch/riscv/kernel/sbi.c | 28 +++ arch/riscv/kernel/traps.c | 7 - arch/riscv/kernel/traps_misaligned.c | 276 ++++++++++++++++++++++----- 8 files changed, 417 insertions(+), 55 deletions(-)