Message ID | 20230622231305.631331-1-heiko@sntech.de |
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Series | RISC-V: T-Head vector handling | |
Message
Heiko Stübner
June 22, 2023, 11:13 p.m. UTC
From: Heiko Stuebner <heiko.stuebner@vrull.eu>
As is widely known the T-Head C9xx cores used for example in the
Allwinner D1 implement an older non-ratified variant of the vector spec.
While userspace will probably have a lot more problems implementing
support for both, on the kernel side the needed changes are actually
somewhat small'ish and can be handled via alternatives somewhat nicely.
With this patchset I could run the same userspace program (picked from
some riscv-vector-test repository) that does some vector additions on
both qemu and a d1-nezha board. On both platforms it ran sucessfully and
even produced the same results.
As can be seen in the todo list, there are 2 places where the changed
SR_VS location still needs to be handled in the next revision
(assembly + ALTERNATIVES + constants + probably stringify resulted in
some grey hair so far already)
ToDo:
- follow along with the base vector patchset
- handle SR_VS access in _save_context and _secondary_start_sbi
changes since v1:
- rebase on top of the merged vector patchset
- add separate patch for "has_vector()" variable
- a number of cleanups
- a comment that T-Head cores do not seem to implement the
vxsat and vxrm fields in the fcsr register
Heiko Stuebner (3):
RISC-V: define the elements of the VCSR vector CSR
RISC-V: move vector-available status into a dedicated variable
RISC-V: add T-Head vector errata handling
arch/riscv/Kconfig.errata | 13 +++
arch/riscv/errata/thead/errata.c | 32 ++++++
arch/riscv/include/asm/csr.h | 29 +++++-
arch/riscv/include/asm/errata_list.h | 45 ++++++++-
arch/riscv/include/asm/vector.h | 144 +++++++++++++++++++++++++--
arch/riscv/kernel/setup.c | 6 ++
arch/riscv/kernel/vector.c | 10 +-
7 files changed, 261 insertions(+), 18 deletions(-)