Message ID | 20230616085513.17632-1-amit.kumar-mahapatra@amd.com |
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Fri, 16 Jun 2023 03:55:19 -0500 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB06.amd.com (10.181.40.147) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Fri, 16 Jun 2023 03:55:19 -0500 Received: from xhdakumarma40u.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.23 via Frontend Transport; Fri, 16 Jun 2023 03:55:15 -0500 From: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com> To: <tudor.ambarus@linaro.org>, <pratyush@kernel.org>, <miquel.raynal@bootlin.com>, <richard@nod.at>, <vigneshr@ti.com>, <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org> CC: <git@amd.com>, <michael@walle.cc>, <linux-mtd@lists.infradead.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <amitrkcian2002@gmail.com>, Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com> Subject: [PATCH v2 0/2] mtd: spi-nor: Avoid setting SRWD bit in SR Date: Fri, 16 Jun 2023 14:25:11 +0530 Message-ID: <20230616085513.17632-1-amit.kumar-mahapatra@amd.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F0:EE_|DM4PR12MB6086:EE_ X-MS-Office365-Filtering-Correlation-Id: 4c8a5cd6-dab0-4db2-2083-08db6e4769f0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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mtd: spi-nor: Avoid setting SRWD bit in SR
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Message
Mahapatra, Amit Kumar
June 16, 2023, 8:55 a.m. UTC
Setting the status register write disable (SRWD) bit in the status register (SR) with WP signal of the flash not connected will configure the SR permanently as read-only. To avoid this a boolean type DT property "broken-wp" is introduced. If this property is defined, the spi-nor doesn't set the SRWD bit in SR while performing flash protection operation. --- BRANCH: for-next Changes in v2: - Modified DT property description to add information about a valid use case. - Added Reviewed-by tag in 1/2. - Updated comment description in 2/2. --- Amit Kumar Mahapatra (2): dt-bindings: mtd: jedec, spi-nor: Add DT property to avoid setting SRWD bit in status register mtd: spi-nor: Avoid setting SRWD bit in SR if WP signal not connected .../devicetree/bindings/mtd/jedec,spi-nor.yaml | 15 +++++++++++++++ drivers/mtd/spi-nor/core.c | 3 +++ drivers/mtd/spi-nor/core.h | 1 + drivers/mtd/spi-nor/swp.c | 9 +++++++-- 4 files changed, 26 insertions(+), 2 deletions(-)