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Tue, 30 May 2023 09:11:56 -0500 From: Suravee Suthikulpanit To: , CC: , , , , , , , , , Suravee Suthikulpanit Subject: [PATCH v3 0/5] iommu/amd: AVIC Interrupt Remapping Improvements Date: Tue, 30 May 2023 10:11:32 -0400 Message-ID: <20230530141137.14376-1-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT044:EE_|CY5PR12MB6370:EE_ X-MS-Office365-Filtering-Correlation-Id: 866f4179-da01-4cff-9ab6-08db6117d586 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: tiflYZ5R7kmWRFGXWP9y0D5UGMx4FhB2+WrEsiMK2WzrmwrsGXbExir1RUbtyNcNgpm6LKtrBWoHLi+rQ1gUNZ2fyII+nXnokN86QnP+NCxT8ZqPMKQWcoC/XKLuYG/k5/V78Uiqiz4jEuEHrv9z2x32koHHu0eT1RdRaz72jj5I+zv2lZPqUac6WcNSwtZE0qwL0a1AvMY4XjQXJm691kQC+5+a8lDpOiQUJXCM0tQm/iTgvA3nlVoqS21edshD5ChFGlS1wIFZnCVfxzZuA3LaDV0k1lAvNLKT9m9XZ7XkBSypO92svk5rXmP6gvZlo+9vc90XVx1AQCP0NDVOy+EMWRO3PS6CKC+kKctBEtVk3AqQnGjF+UtkbNAJlOIr3aiYLKrfkCbskzgNpXrBE4p0cLFaJCT1WLICjXxitJiwZM2wAAF/Wg/g1Pk28ElhsmAkRp4lpOkaAsGFJydrs3q4ATVJPbgbWW751B19Lv1UaD2Dv8vYJZMiAaf2Q5UPtJXcFpFPPk4O7jex9pGCTC1PO8xmDCLRZ2don9oqYWMi7cdP8qoiDhIegQDHBTcL7GHYrD25rdGcH/9dxTWwnwQSkqo5tcSyDb2dtDnT4qf+sl6q46XbYBAX/1bHZU9+86JEzWpZ+VElZrYzmHUkaLbxcyImQGDDJukE0KqDjsYJLbPvf/R4XY9aIQFn6QvYtmIpWe3Dh95clmu9hlUcjl+uttzvQii+j+vLwIC1ajfm7xXMYaU1dtRa7NdRbZ9AzadEhpqRigfmO2PuZSg6ptjuaP0x/6f1qBDpHhSOOz0= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(346002)(39860400002)(396003)(376002)(136003)(451199021)(36840700001)(46966006)(40470700004)(40460700003)(40480700001)(26005)(336012)(426003)(47076005)(1076003)(82310400005)(36756003)(16526019)(186003)(41300700001)(36860700001)(83380400001)(4326008)(316002)(70206006)(70586007)(478600001)(2616005)(8676002)(5660300002)(8936002)(110136005)(54906003)(86362001)(44832011)(356005)(82740400003)(81166007)(7696005)(6666004)(2906002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 May 2023 14:11:59.6005 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 866f4179-da01-4cff-9ab6-08db6117d586 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT044.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6370 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1767329170137470020?= X-GMAIL-MSGID: =?utf-8?q?1767329170137470020?= For IOMMU AVIC, the IOMMU driver needs to keep track of vcpu scheduling changes, and updates interrupt remapping table entry (IRTE) accordingly. The IRTE is normally cached by the hardware, which requires the IOMMU driver to issue IOMMU IRT invalidation command and wait for completion everytime it updates the table. Enabling IOMMU AVIC on a large scale system with lots of vcpus and VFIO pass-through devices running interrupt-intensive workload, it could result in high IRT invalidation rate. In such case, the overhead from IRT invalidation could outweigh the benefit of IRTE caching. Therefore, introduce a new AMD IOMMU driver option "amd_iommu=irtcachedis" to allow disabling IRTE caching, and avoid the need for IRTE invalidation. Patch 1,2 prepare the AMD IOMMU driver to support IRT cache disabling. Patch 3,4 introduce IRT cache disabling support Patch 5 improves the code path in IOMMU driver for updating vcpu scheduling for AVIC. Thank you, Suravee Changes from V2 (https://lore.kernel.org/linux-iommu/rlurmw6n6eyyhtnfr6wva6azur2gvgcrdn4mvykr3nvsosj5py@ieaivyv6cqrv/T/) * Added Reviewed-by and Sign-off-by. * Patch 4: Reword the commit summary (per Jerry suggestion). Changes from V1 (https://lore.kernel.org/lkml/20230509111646.369661-1-suravee.suthikulpanit@amd.com/T/) * Patch 3: Add logic to clean up the IRTE cache disabling and handle kdump code path (per Alejandro) Joao Martins (1): iommu/amd: Switch amd_iommu_update_ga() to use modify_irte_ga() Suravee Suthikulpanit (4): iommu/amd: Remove the unused struct amd_ir_data.ref iommu/amd: Introduce Disable IRTE Caching Support iommu/amd: Do not Invalidate IRT when IRTE caching is disabled iommu/amd: Improving Interrupt Remapping Table Invalidation .../admin-guide/kernel-parameters.txt | 1 + drivers/iommu/amd/amd_iommu_types.h | 7 +- drivers/iommu/amd/init.c | 38 +++++++- drivers/iommu/amd/iommu.c | 97 ++++++++++--------- 4 files changed, 94 insertions(+), 49 deletions(-)