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Wed, 24 May 2023 18:18:34 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 34OIIX38006797 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 24 May 2023 18:18:33 GMT Received: from hu-jkona-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Wed, 24 May 2023 11:18:28 -0700 From: Jagadeesh Kona <quic_jkona@quicinc.com> To: Andy Gross <agross@kernel.org>, Bjorn Andersson <andersson@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org> CC: Konrad Dybcio <konrad.dybcio@linaro.org>, <linux-arm-msm@vger.kernel.org>, <linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, Taniya Das <quic_tdas@quicinc.com>, "Jagadeesh Kona" <quic_jkona@quicinc.com>, Satya Priya Kakitapalli <quic_skakitap@quicinc.com>, Imran Shaik <quic_imrashai@quicinc.com>, "Ajit Pandey" <quic_ajipan@quicinc.com> Subject: [PATCH V2 0/3] Add graphics clock controller support for SM8550 Date: Wed, 24 May 2023 23:47:57 +0530 Message-ID: <20230524181800.28717-1-quic_jkona@quicinc.com> X-Mailer: git-send-email 2.40.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: TrTBY1l1jHWXoJTcan_iNx9LYTE40F0E X-Proofpoint-GUID: TrTBY1l1jHWXoJTcan_iNx9LYTE40F0E X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-05-24_13,2023-05-24_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 adultscore=0 bulkscore=0 spamscore=0 malwarescore=0 lowpriorityscore=0 suspectscore=0 mlxlogscore=861 mlxscore=0 phishscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305240151 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1766802458555662351?= X-GMAIL-MSGID: =?utf-8?q?1766802458555662351?= |
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Add graphics clock controller support for SM8550
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Message
Jagadeesh Kona
May 24, 2023, 6:17 p.m. UTC
Add bindings, driver and devicetree node for graphics clock controller on SM8550. Depends on [1] and [2] for PLL_TEST_CTL_U2 programming and SM8450 GPUCC YAML file [1] https://patchwork.kernel.org/project/linux-clk/list/?series=750700 [2] https://patchwork.kernel.org/project/linux-clk/list/?series=748562 Jagadeesh Kona (3): dt-bindings: clock: qcom: Add SM8550 graphics clock controller clk: qcom: gpucc-sm8550: Add support for graphics clock controller arm64: dts: qcom: sm8550: Add graphics clock controller .../bindings/clock/qcom,sm8450-gpucc.yaml | 2 + arch/arm64/boot/dts/qcom/sm8550.dtsi | 12 + drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gpucc-sm8550.c | 611 ++++++++++++++++++ include/dt-bindings/clock/qcom,sm8550-gpucc.h | 48 ++ 6 files changed, 682 insertions(+) create mode 100644 drivers/clk/qcom/gpucc-sm8550.c create mode 100644 include/dt-bindings/clock/qcom,sm8550-gpucc.h
Comments
On Wed, 24 May 2023 23:47:57 +0530, Jagadeesh Kona wrote: > Add bindings, driver and devicetree node for graphics clock controller on SM8550. > > Depends on [1] and [2] for PLL_TEST_CTL_U2 programming and SM8450 GPUCC YAML file > [1] https://patchwork.kernel.org/project/linux-clk/list/?series=750700 > [2] https://patchwork.kernel.org/project/linux-clk/list/?series=748562 > > Jagadeesh Kona (3): > dt-bindings: clock: qcom: Add SM8550 graphics clock controller > clk: qcom: gpucc-sm8550: Add support for graphics clock controller > arm64: dts: qcom: sm8550: Add graphics clock controller > > [...] Applied, thanks! [3/3] arm64: dts: qcom: sm8550: Add graphics clock controller commit: 9f7579423d2d619064dc84cfa8068e3c83b09e3f Best regards,