[V6,00/21] Add basic ACPI support for RISC-V

  This patch series enables the basic ACPI infrastructure for RISC-V.
Supporting external interrupt controllers is in progress and hence it is
tested using poll based HVC SBI console and RAM disk.

The first patch in this series is one of the patch from Jisheng's
series [1] which is not merged yet. This patch is required to support
ACPI since efi_init() which gets called before sbi_init() can enable
static branches and hits a panic.

Below are two ECRs approved by ASWG.
RINTC - https://drive.google.com/file/d/1R6k4MshhN3WTT-hwqAquu5nX6xSEqK2l/view
RHCT - https://drive.google.com/file/d/1nP3nFiH4jkPMp6COOxP6123DCZKR-tia/view


Changes since V5:
	1) Reordered commits in the series to avoid intermediate build failure reported by Conor.
	2) Updated hisilicon driver patch as per feedback from Herbert Xu.
	3) Rebased to 6.4-rc2

Changes since V4:
	1) Rebased with 6.4-rc1 which has ACPICA patches now.
	2) Split cpufeature.c patch into two by adding patch 2/7 from Conor's series [2]
	3) Updated caching RINTC logic to avoid global.
	4) Added driver patches to enable allmodconfig build at the start of the series.
	5) Updated tags

Changes since V3:
	1) Added two more driver patches to workaround allmodconfig build failure.
	2) Separated removal of riscv_of_processor_hartid() to a different patch.
	3) Addressed Conor's feedback.
	4) Rebased to v6.3-rc5 and added latest tags

Changes since V2:
	1) Dropped ACPI_PROCESSOR patch.
	2) Added new patch to print debug info of RISC-V INTC in MADT
	3) Addressed other comments from Drew.
	4) Rebased and updated tags

Changes since V1:
	1) Dropped PCI changes and instead added dummy interfaces just to enable
	   building ACPI core when CONFIG_PCI is enabled. Actual PCI changes will
	   be added in future along with external interrupt controller support
	   in ACPI.
	2) Squashed couple of patches so that new code added gets built in each
	   commit.
	3) Fixed the missing wake_cpu code in timer refactor patch as pointed by
	   Conor
	4) Fixed an issue with SMP disabled.
	5) Addressed other comments from Conor.
	6) Updated documentation patch as per feedback from Sanjaya.
	7) Fixed W=1 and checkpatch --strict issues.
	8) Added ACK/RB tags

[1] https://lore.kernel.org/all/20220821140918.3613-1-jszhang@kernel.org/
[2] https://lore.kernel.org/linux-riscv/20230504-divisive-unsavory-5a2ff0c3c2d1@spud/

These changes are available at
https://github.com/vlsunil/linux/commits/acpi_b1_us_review_v6

Testing:
1) Build latest Qemu 

2) Build EDK2 as per instructions in
https://github.com/vlsunil/riscv-uefi-edk2-docs/wiki/RISC-V-Qemu-Virt-support

3) Build Linux after enabling SBI HVC and SBI earlycon
CONFIG_RISCV_SBI_V01=y
CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
CONFIG_HVC_RISCV_SBI=y

4) Build buildroot.

Run with below command.
qemu-system-riscv64   -nographic \
-drive file=Build/RiscVVirtQemu/RELEASE_GCC5/FV/RISCV_VIRT.fd,if=pflash,format=raw,unit=1 \
-machine virt -smp 16 -m 2G \
-kernel arch/riscv/boot/Image \
-initrd buildroot/output/images/rootfs.cpio \
-append "root=/dev/ram ro console=hvc0 earlycon=sbi"


Jisheng Zhang (1):
  riscv: move sbi_init() earlier before jump_label_init()

Sunil V L (20):
  platform/surface: Disable for RISC-V
  crypto: hisilicon/qm: Fix to enable build with RISC-V clang
  ACPI: tables: Print RINTC information when MADT is parsed
  ACPI: OSL: Make should_use_kmap() 0 for RISC-V
  RISC-V: Add support to build the ACPI core
  ACPI: processor_core: RISC-V: Enable mapping processor to the hartid
  RISC-V: Add ACPI initialization in setup_arch()
  RISC-V: ACPI: Cache and retrieve the RINTC structure
  drivers/acpi: RISC-V: Add RHCT related code
  RISC-V: smpboot: Create wrapper setup_smp()
  RISC-V: smpboot: Add ACPI support in setup_smp()
  RISC-V: only iterate over possible CPUs in ISA string parser
  RISC-V: cpufeature: Add ACPI support in riscv_fill_hwcap()
  RISC-V: cpu: Enable cpuinfo for ACPI systems
  irqchip/riscv-intc: Add ACPI support
  clocksource/timer-riscv: Refactor riscv_timer_init_dt()
  clocksource/timer-riscv: Add ACPI support
  RISC-V: time.c: Add ACPI support for time_init()
  RISC-V: Enable ACPI in defconfig
  MAINTAINERS: Add entry for drivers/acpi/riscv

 .../admin-guide/kernel-parameters.txt         |   8 +-
 MAINTAINERS                                   |   7 +
 arch/riscv/Kconfig                            |   5 +
 arch/riscv/configs/defconfig                  |   1 +
 arch/riscv/include/asm/acenv.h                |  11 +
 arch/riscv/include/asm/acpi.h                 |  84 ++++++
 arch/riscv/include/asm/cpu.h                  |   8 +
 arch/riscv/kernel/Makefile                    |   1 +
 arch/riscv/kernel/acpi.c                      | 251 ++++++++++++++++++
 arch/riscv/kernel/cpu.c                       |  30 ++-
 arch/riscv/kernel/cpufeature.c                |  42 ++-
 arch/riscv/kernel/setup.c                     |  11 +-
 arch/riscv/kernel/smpboot.c                   |  77 +++++-
 arch/riscv/kernel/time.c                      |  25 +-
 drivers/acpi/Makefile                         |   2 +
 drivers/acpi/osl.c                            |   2 +-
 drivers/acpi/processor_core.c                 |  29 ++
 drivers/acpi/riscv/Makefile                   |   2 +
 drivers/acpi/riscv/rhct.c                     |  83 ++++++
 drivers/acpi/tables.c                         |  10 +
 drivers/clocksource/timer-riscv.c             |  92 ++++---
 drivers/crypto/hisilicon/qm.c                 |   5 +
 drivers/irqchip/irq-riscv-intc.c              |  70 +++--
 drivers/platform/surface/aggregator/Kconfig   |   2 +-
 24 files changed, 772 insertions(+), 86 deletions(-)
 create mode 100644 arch/riscv/include/asm/acenv.h
 create mode 100644 arch/riscv/include/asm/acpi.h
 create mode 100644 arch/riscv/include/asm/cpu.h
 create mode 100644 arch/riscv/kernel/acpi.c
 create mode 100644 drivers/acpi/riscv/Makefile
 create mode 100644 drivers/acpi/riscv/rhct.c
  

On Mon, 15 May 2023 11:19:07 +0530, Sunil V L wrote:
> This patch series enables the basic ACPI infrastructure for RISC-V.
> Supporting external interrupt controllers is in progress and hence it is
> tested using poll based HVC SBI console and RAM disk.
> 
> The first patch in this series is one of the patch from Jisheng's
> series [1] which is not merged yet. This patch is required to support
> ACPI since efi_init() which gets called before sbi_init() can enable
> static branches and hits a panic.
> 
> [...]

Applied, thanks!

[01/21] riscv: move sbi_init() earlier before jump_label_init()
        https://git.kernel.org/palmer/c/24fc18087f42
[02/21] platform/surface: Disable for RISC-V
        https://git.kernel.org/palmer/c/7f2e20459b28
[03/21] crypto: hisilicon/qm: Fix to enable build with RISC-V clang
        https://git.kernel.org/palmer/c/fbb995a7b27c
[04/21] ACPI: tables: Print RINTC information when MADT is parsed
        https://git.kernel.org/palmer/c/4d02d88d2b92
[05/21] ACPI: OSL: Make should_use_kmap() 0 for RISC-V
        https://git.kernel.org/palmer/c/214c236223b8
[06/21] RISC-V: Add support to build the ACPI core
        https://git.kernel.org/palmer/c/a91a9ffbd3a5
[07/21] ACPI: processor_core: RISC-V: Enable mapping processor to the hartid
        https://git.kernel.org/palmer/c/8b7809e28952
[08/21] RISC-V: Add ACPI initialization in setup_arch()
        https://git.kernel.org/palmer/c/724f4c0df766
[09/21] RISC-V: ACPI: Cache and retrieve the RINTC structure
        https://git.kernel.org/palmer/c/f99561199470
[10/21] drivers/acpi: RISC-V: Add RHCT related code
        https://git.kernel.org/palmer/c/e6b9d8eddb17
[11/21] RISC-V: smpboot: Create wrapper setup_smp()
        https://git.kernel.org/palmer/c/61946127ab49
[12/21] RISC-V: smpboot: Add ACPI support in setup_smp()
        https://git.kernel.org/palmer/c/ce92546cd637
[13/21] RISC-V: only iterate over possible CPUs in ISA string parser
        https://git.kernel.org/palmer/c/914d6f44fc50
[14/21] RISC-V: cpufeature: Add ACPI support in riscv_fill_hwcap()
        https://git.kernel.org/palmer/c/396c018332a1
[15/21] RISC-V: cpu: Enable cpuinfo for ACPI systems
        https://git.kernel.org/palmer/c/0b144c818989
[16/21] irqchip/riscv-intc: Add ACPI support
        https://git.kernel.org/palmer/c/7023b9d83f03
[17/21] clocksource/timer-riscv: Refactor riscv_timer_init_dt()
        https://git.kernel.org/palmer/c/cd12d206685a
[18/21] clocksource/timer-riscv: Add ACPI support
        https://git.kernel.org/palmer/c/21f4f92410dc
[19/21] RISC-V: time.c: Add ACPI support for time_init()
        https://git.kernel.org/palmer/c/714aa1d1c8ca
[20/21] RISC-V: Enable ACPI in defconfig
        https://git.kernel.org/palmer/c/0b8e15ca0082

Best regards,
  

Hello:

This series was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer@rivosinc.com>:

On Mon, 15 May 2023 11:19:07 +0530 you wrote:
> This patch series enables the basic ACPI infrastructure for RISC-V.
> Supporting external interrupt controllers is in progress and hence it is
> tested using poll based HVC SBI console and RAM disk.
> 
> The first patch in this series is one of the patch from Jisheng's
> series [1] which is not merged yet. This patch is required to support
> ACPI since efi_init() which gets called before sbi_init() can enable
> static branches and hits a panic.
> 
> [...]

Here is the summary with links:
  - [V6,01/21] riscv: move sbi_init() earlier before jump_label_init()
    https://git.kernel.org/riscv/c/24fc18087f42
  - [V6,02/21] platform/surface: Disable for RISC-V
    https://git.kernel.org/riscv/c/7f2e20459b28
  - [V6,03/21] crypto: hisilicon/qm: Fix to enable build with RISC-V clang
    https://git.kernel.org/riscv/c/fbb995a7b27c
  - [V6,04/21] ACPI: tables: Print RINTC information when MADT is parsed
    https://git.kernel.org/riscv/c/4d02d88d2b92
  - [V6,05/21] ACPI: OSL: Make should_use_kmap() 0 for RISC-V
    https://git.kernel.org/riscv/c/214c236223b8
  - [V6,06/21] RISC-V: Add support to build the ACPI core
    https://git.kernel.org/riscv/c/a91a9ffbd3a5
  - [V6,07/21] ACPI: processor_core: RISC-V: Enable mapping processor to the hartid
    https://git.kernel.org/riscv/c/8b7809e28952
  - [V6,08/21] RISC-V: Add ACPI initialization in setup_arch()
    https://git.kernel.org/riscv/c/724f4c0df766
  - [V6,09/21] RISC-V: ACPI: Cache and retrieve the RINTC structure
    https://git.kernel.org/riscv/c/f99561199470
  - [V6,10/21] drivers/acpi: RISC-V: Add RHCT related code
    https://git.kernel.org/riscv/c/e6b9d8eddb17
  - [V6,11/21] RISC-V: smpboot: Create wrapper setup_smp()
    https://git.kernel.org/riscv/c/61946127ab49
  - [V6,12/21] RISC-V: smpboot: Add ACPI support in setup_smp()
    https://git.kernel.org/riscv/c/ce92546cd637
  - [V6,13/21] RISC-V: only iterate over possible CPUs in ISA string parser
    https://git.kernel.org/riscv/c/914d6f44fc50
  - [V6,14/21] RISC-V: cpufeature: Add ACPI support in riscv_fill_hwcap()
    https://git.kernel.org/riscv/c/396c018332a1
  - [V6,15/21] RISC-V: cpu: Enable cpuinfo for ACPI systems
    https://git.kernel.org/riscv/c/0b144c818989
  - [V6,16/21] irqchip/riscv-intc: Add ACPI support
    https://git.kernel.org/riscv/c/7023b9d83f03
  - [V6,17/21] clocksource/timer-riscv: Refactor riscv_timer_init_dt()
    https://git.kernel.org/riscv/c/cd12d206685a
  - [V6,18/21] clocksource/timer-riscv: Add ACPI support
    https://git.kernel.org/riscv/c/21f4f92410dc
  - [V6,19/21] RISC-V: time.c: Add ACPI support for time_init()
    https://git.kernel.org/riscv/c/714aa1d1c8ca
  - [V6,20/21] RISC-V: Enable ACPI in defconfig
    https://git.kernel.org/riscv/c/0b8e15ca0082
  - [V6,21/21] MAINTAINERS: Add entry for drivers/acpi/riscv
    https://git.kernel.org/riscv/c/cc9e654a7e81

You are awesome, thank you!
  

On Fri, 02 Jun 2023 07:57:57 PDT (-0700), Palmer Dabbelt wrote:
>
> On Mon, 15 May 2023 11:19:07 +0530, Sunil V L wrote:
>> This patch series enables the basic ACPI infrastructure for RISC-V.
>> Supporting external interrupt controllers is in progress and hence it is
>> tested using poll based HVC SBI console and RAM disk.
>>
>> The first patch in this series is one of the patch from Jisheng's
>> series [1] which is not merged yet. This patch is required to support
>> ACPI since efi_init() which gets called before sbi_init() can enable
>> static branches and hits a panic.
>>
>> [...]
>
> Applied, thanks!
>
> [01/21] riscv: move sbi_init() earlier before jump_label_init()
>         https://git.kernel.org/palmer/c/24fc18087f42
> [02/21] platform/surface: Disable for RISC-V
>         https://git.kernel.org/palmer/c/7f2e20459b28
> [03/21] crypto: hisilicon/qm: Fix to enable build with RISC-V clang
>         https://git.kernel.org/palmer/c/fbb995a7b27c
> [04/21] ACPI: tables: Print RINTC information when MADT is parsed
>         https://git.kernel.org/palmer/c/4d02d88d2b92
> [05/21] ACPI: OSL: Make should_use_kmap() 0 for RISC-V
>         https://git.kernel.org/palmer/c/214c236223b8
> [06/21] RISC-V: Add support to build the ACPI core
>         https://git.kernel.org/palmer/c/a91a9ffbd3a5
> [07/21] ACPI: processor_core: RISC-V: Enable mapping processor to the hartid
>         https://git.kernel.org/palmer/c/8b7809e28952
> [08/21] RISC-V: Add ACPI initialization in setup_arch()
>         https://git.kernel.org/palmer/c/724f4c0df766
> [09/21] RISC-V: ACPI: Cache and retrieve the RINTC structure
>         https://git.kernel.org/palmer/c/f99561199470
> [10/21] drivers/acpi: RISC-V: Add RHCT related code
>         https://git.kernel.org/palmer/c/e6b9d8eddb17
> [11/21] RISC-V: smpboot: Create wrapper setup_smp()
>         https://git.kernel.org/palmer/c/61946127ab49
> [12/21] RISC-V: smpboot: Add ACPI support in setup_smp()
>         https://git.kernel.org/palmer/c/ce92546cd637
> [13/21] RISC-V: only iterate over possible CPUs in ISA string parser
>         https://git.kernel.org/palmer/c/914d6f44fc50
> [14/21] RISC-V: cpufeature: Add ACPI support in riscv_fill_hwcap()
>         https://git.kernel.org/palmer/c/396c018332a1
> [15/21] RISC-V: cpu: Enable cpuinfo for ACPI systems
>         https://git.kernel.org/palmer/c/0b144c818989
> [16/21] irqchip/riscv-intc: Add ACPI support
>         https://git.kernel.org/palmer/c/7023b9d83f03
> [17/21] clocksource/timer-riscv: Refactor riscv_timer_init_dt()
>         https://git.kernel.org/palmer/c/cd12d206685a
> [18/21] clocksource/timer-riscv: Add ACPI support
>         https://git.kernel.org/palmer/c/21f4f92410dc
> [19/21] RISC-V: time.c: Add ACPI support for time_init()
>         https://git.kernel.org/palmer/c/714aa1d1c8ca
> [20/21] RISC-V: Enable ACPI in defconfig
>         https://git.kernel.org/palmer/c/0b8e15ca0082

I applied the MAINTAINERS entry too, it just had a conflict and it looks 
like my attempt at juggling it didn't play nice with the thanks message.  
Everything's on top of rc1 because that's what my for-next is based on.

I also don't yet have any testing for the ACPI stuff, but hopefully I'll 
get around to adding some.  We should probably add it to the patchwwork 
CI as well.

>
> Best regards,
  

On Fri, Jun 02, 2023 at 08:11:04AM -0700, Palmer Dabbelt wrote:
> On Fri, 02 Jun 2023 07:57:57 PDT (-0700), Palmer Dabbelt wrote:

> I also don't yet have any testing for the ACPI stuff, but hopefully I'll get
> around to adding some.  We should probably add it to the patchwwork CI as
> well.

Yeah, just like DT testing should be added too! I am planning on doing
some work on that front next week, hopefully I make good on my word...

Cheers,
Conor.

Also, having ACPI support in means we now need
https://lore.kernel.org/all/tencent_B30EED51C7235CA1988890E5C658BE35C107@qq.com/
to be compliant with the ECR. It doesn't apply as-is, so I will add a
Fixes tag & rebase.
  

On Fri, Jun 02, 2023 at 04:50:49PM +0100, Conor Dooley wrote:
> On Fri, Jun 02, 2023 at 08:11:04AM -0700, Palmer Dabbelt wrote:
> > On Fri, 02 Jun 2023 07:57:57 PDT (-0700), Palmer Dabbelt wrote:
> 
> > I also don't yet have any testing for the ACPI stuff, but hopefully I'll get
> > around to adding some.  We should probably add it to the patchwwork CI as
> > well.
> 
> Yeah, just like DT testing should be added too! I am planning on doing
> some work on that front next week, hopefully I make good on my word...
> 
> Cheers,
> Conor.
> 
> Also, having ACPI support in means we now need
> https://lore.kernel.org/all/tencent_B30EED51C7235CA1988890E5C658BE35C107@qq.com/
> to be compliant with the ECR. It doesn't apply as-is, so I will add a
> Fixes tag & rebase.

Nevermind, doesn't need a rebase - it applies with `b4 am -3` ;)

Cheers,
Conor.