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[2620:137:e000::1:20]) by mx.google.com with ESMTP id i6-20020a056a00004600b00643bac6f81esi2925062pfk.16.2023.05.09.10.37.52; Tue, 09 May 2023 10:38:05 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=hPAsr7AV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232812AbjEIRWX (ORCPT + 99 others); Tue, 9 May 2023 13:22:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37056 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234262AbjEIRWT (ORCPT ); Tue, 9 May 2023 13:22:19 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 92B841BCB; Tue, 9 May 2023 10:22:15 -0700 (PDT) Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 349GguCC020103; Tue, 9 May 2023 17:22:12 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : mime-version : content-type; s=qcppdkim1; bh=bbvAu1RMUs5Yto3tyQpfnpR0HvMNfvh8+ycuopiZ1Wk=; b=hPAsr7AV6ySVkGDAYZeOmdoSrRqy0coffiTJSrEcbCTO5igzGlMSeqUFnJRCksEQOXVp DY6m/8fNTUvh6sIGcuyfL0OkTVneuLdnNPG3mnScXuc3Rg6xqAC0FM5UuVSi8+UeaEqH Eb2gvlMjbJZ+HB6mFHePz0oiyiJGjGwPjD/k5MFeaqbrDlsyCukuoAmoDGchLflLrpsg TBwsjJ22QYq9BnObl1HFLdQMzLJXu11KahQOBwCEVaY4oOd+MInrlSuUaNLZk8fyqSCN m4QZMUzln6UQzIUdND8qCklG0EPtyZ19jAVfHA8snhFuFurOHYQunbJ2JhrKEr8/V4s1 5Q== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3qf77g2g58-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 09 May 2023 17:22:11 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 349HMBgO030723 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 9 May 2023 17:22:11 GMT Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Tue, 9 May 2023 10:22:06 -0700 From: Taniya Das To: Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Andy Gross , Michael Turquette CC: Bjorn Andersson , Konrad Dybcio , Taniya Das , , , , , , Subject: [PATCH V4 0/3] Add video clock controller driver for SM8450 Date: Tue, 9 May 2023 22:51:45 +0530 Message-ID: <20230509172148.7627-1-quic_tdas@quicinc.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: A9g44H6dr-eutw3XYrkTSMd18ffhz6g9 X-Proofpoint-ORIG-GUID: A9g44H6dr-eutw3XYrkTSMd18ffhz6g9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-09_10,2023-05-05_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 mlxlogscore=712 malwarescore=0 clxscore=1015 mlxscore=0 suspectscore=0 priorityscore=1501 bulkscore=0 lowpriorityscore=0 spamscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305090144 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765439056263827696?= X-GMAIL-MSGID: =?utf-8?q?1765439056263827696?= Add bindings, driver and DT node for video clock controller on SM8450. Taniya Das (3): dt-bindings: clock: qcom: Add SM8450 video clock controller clk: qcom: videocc-sm8450: Add video clock controller driver for SM8450 arm64: dts: qcom: sm8450: Add video clock controller .../bindings/clock/qcom,sm8450-videocc.yaml | 77 +++ arch/arm64/boot/dts/qcom/sm8450.dtsi | 12 + drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/videocc-sm8450.c | 461 ++++++++++++++++++ .../dt-bindings/clock/qcom,sm8450-videocc.h | 38 ++ 6 files changed, 598 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml create mode 100644 drivers/clk/qcom/videocc-sm8450.c create mode 100644 include/dt-bindings/clock/qcom,sm8450-videocc.h