From patchwork Mon Apr 17 09:16:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ilpo_J=C3=A4rvinen?= X-Patchwork-Id: 8281 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1987337vqo; Mon, 17 Apr 2023 02:26:20 -0700 (PDT) X-Google-Smtp-Source: AKy350ZaAAe7784y4+71B3MTaq0MeisqQYycR/E2u7y9NCRKj+OVZRNTzPxLSN8B1E4iyYPHVDHu X-Received: by 2002:a05:6a00:1a0d:b0:636:f899:4696 with SMTP id g13-20020a056a001a0d00b00636f8994696mr19794817pfv.24.1681723579940; Mon, 17 Apr 2023 02:26:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681723579; cv=none; d=google.com; s=arc-20160816; b=jzqeCJy/XHbjCHfy3OkHQwU6kSYVyud8EjT5NUK1MkfkN5399eyD7ZZQDYuM7U8OEV HuyMXleT/GyeMcvTWMY1/+WhpDVfKbOO4A7pZfhxGESl42+fLR/xiU5Xf6ckTBv+srr5 pdoqnzM6gw/gaEeNjtmT8tIKIRlPX4iiqzQ02qbvyZLLHz4hbvzrV7J7MH3yqfeKn9TF B3Ar5BiZzNTeswXIuhqHSDx2tfO7gInptBjGQAsChrCDniTJWfIHhELr8ns1vnLTEPlm auKfKOiSGkNjCkizYIFurZQwp4EHMtQXFlqClMBAWZiFsL9j+/C7ILx7eyR08sRSPdYA mlKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=FD/A2OUj74bAn44LsrtZ9jIw7yREEh/kLm/VI9Lvlik=; b=xPESWUD7UVirHHVnjYl1h35cQWWI+qHMdxuKahGFSou+mHDThs6/tqIls0Yq7lS2bK 7NN4P81UZZ6HEWtnoMwGh78M4gOgcjW5P3+tJB7FyZBe6s2rn50hWEyNUANwPswyAEPy u/YERoGLKOzgv6KQX1JccisTYFURJlSJ7URCJ6bser4LiKma98aEfqi2Iaw8uQOHowGf NxGJqrBtGNYPakLR9LKM+/rYhbugBof1AWpszpQMLnLVI/RNQWr3od5vHfHIJnheX4nk /k1fnTB92XC7Qn9c5bEFf/2lO95xRVDUqoVqnQnOvK2v8HfTvCrdvGqc87G2D1IG4hiH zVHw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=M4JAgf5d; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id s125-20020a625e83000000b0063806e9892fsi11398783pfb.243.2023.04.17.02.26.08; Mon, 17 Apr 2023 02:26:19 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=M4JAgf5d; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229519AbjDQJQl (ORCPT + 99 others); Mon, 17 Apr 2023 05:16:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44418 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230181AbjDQJQj (ORCPT ); Mon, 17 Apr 2023 05:16:39 -0400 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1815849CA; Mon, 17 Apr 2023 02:16:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681722998; x=1713258998; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=4KF2KAjyrsD3AOzxtejb2jOCrRVS9sKyae+V2KcLQzw=; b=M4JAgf5dnOOY1ZPwGh5bixZn7xrT9C8iz0zNJfuyUH0WePNTzChh+03N 44o6oMxrLgVEywGY4xnRMe5qxY/c43/hg2RqO43NAdlpFALGojld0DCrC 9I7dZ/Fdi0pgwg2r3w3++LemBfCMAYWUTuMaqmkln8BpSZtHH9vAKJC4A 5QPwJ7dl7v3Y6rNFGkUniE6tIuIh020lkwDydRwxN9C8IyOJGdryjTmYK RWqh/HqJ2hSSGpnFPpQgvDliSlknNdTM+81c6zL4pCBzcsQGSaz1gP41L k0Lr41xCzVqDnEVT9WSFVmE76s4dQr1U378skY4S2lXKxWYklIdyXZsXH Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10682"; a="342338676" X-IronPort-AV: E=Sophos;i="5.99,203,1677571200"; d="scan'208";a="342338676" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Apr 2023 02:16:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10682"; a="690595451" X-IronPort-AV: E=Sophos;i="5.99,203,1677571200"; d="scan'208";a="690595451" Received: from anicosix-mobl2.ger.corp.intel.com (HELO ijarvine-MOBL2.ger.corp.intel.com) ([10.249.35.34]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Apr 2023 02:16:34 -0700 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: Xu Yilun , Wu Hao , Tom Rix , Moritz Fischer , linux-fpga@vger.kernel.org, Lee Jones , Jean Delvare , Guenter Roeck , Russ Weight Cc: linux-hwmon@vger.kernel.org, LKML , =?utf-8?q?Ilpo_J=C3=A4rvinen?= Subject: [PATCH v2 0/4] intel-m10-bmc: Manage register access to control delay during sec update Date: Mon, 17 Apr 2023 12:16:15 +0300 Message-Id: <20230417091619.14134-1-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763414985055338359?= X-GMAIL-MSGID: =?utf-8?q?1763414985055338359?= Manage handshake register access on Max 10 FPGA cards that have a major slowdown on reading handshake registers during secure update prepare and write phases. The problem does not occur with PMCI-based cards. The first patch which moves Max M10 symbols into own namespace is otherwise independent of the other changes but it would conflict with this series if sent as separate change. Thus, it's part of this series to give the patches a well-defined order. Ilpo Järvinen (4): mfd: intel-m10-bmc: Move core symbols to own namespace mfd: intel-m10-bmc: Create m10bmc_sys_update_bits() mfd: intel-m10-bmc: Move m10bmc_sys_read() away from header mfd: intel-m10-bmc: Manage access to MAX 10 fw handshake registers drivers/fpga/intel-m10-bmc-sec-update.c | 47 +++++++------ drivers/hwmon/intel-m10-bmc-hwmon.c | 1 + drivers/mfd/intel-m10-bmc-core.c | 90 ++++++++++++++++++++++++- drivers/mfd/intel-m10-bmc-pmci.c | 1 + drivers/mfd/intel-m10-bmc-spi.c | 15 +++++ include/linux/mfd/intel-m10-bmc.h | 43 ++++++++---- 6 files changed, 163 insertions(+), 34 deletions(-)