Message ID | 20230417065005.24967-1-yu.tu@amlogic.com |
---|---|
Headers |
Return-Path: <linux-kernel-owner@vger.kernel.org> Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1926038vqo; Sun, 16 Apr 2023 23:52:21 -0700 (PDT) X-Google-Smtp-Source: AKy350a5GJthlL8DeHD84TNmcr2f1wqE71mD1zuwfqepfOwqBZHUVpk8SFLpIhcjsJuIuIsjXnNF X-Received: by 2002:a05:6a00:2d28:b0:63b:8963:d952 with SMTP id fa40-20020a056a002d2800b0063b8963d952mr4790319pfb.17.1681714341445; Sun, 16 Apr 2023 23:52:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681714341; cv=none; d=google.com; s=arc-20160816; b=wqh8MPM+tH69PRWu+jmFib4l9MrNZ12mRuqjHwSHan6S23RirFaYbDEKDacybpEyOb k3kbXGMf28WMQgqDK+FDQ1xLihcXCXLg66EinvFw1dBvf57Kul4MAH7QnZd9jgOovIyR BTolmH0ewwoay8QUwwwXzdhFAfxjwOciB+A5IbqU8SiXTvFKhdkcWUSCzBrSUICyx53x GE/Ly3oYBIU7JwuRLvt+yHS00qDD5G8d5tFjhALwjRYwEjNHi27svdsSUztzV0Pu4XMq zvY5YEd9Z+Dirh5mRIMyyxKkpy9s5QEzADCntf+2DaGjzvR+7Wmsg+iGjj5kQzqBSskY CHQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=6hC6AiiUBQuwIjhbkVv3YcBZC2NCmvWUMn9vRrdG0Ls=; b=xU3515ejt5/2hvd6BgHmKn/qKMD+UPwBGOA/KtHIGxM7a4/23Ye4FW31J/r7bZM0Fl MSsxe/xjIy+QdvWDcwiMICDSxfvDf26TAPIQ6N7LtCNFNgOJjtlfQg/ezU1TC9EQb/jl 6cnM9BfmvkpxpP5AA87j8b9e/trr5C53WTmFGrL2T5HJxOTgXG7ZnM9lak29DZAeSc7L /UXHBRkiGkpq1M42j2DrcvIGiIycHWuKb67VkcaSBavN44xuZ8makHcnkY77OoBDN0pu X9Vzjn2hjiqZzMpKe1nA/F/6uUpvXP67AlSxQ+y9VEGQZfilqtlr/VkCVpyObWCWl4cq q1LQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id d137-20020a621d8f000000b0062dd1d1c48csi10731843pfd.377.2023.04.16.23.52.06; Sun, 16 Apr 2023 23:52:21 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230231AbjDQGvk (ORCPT <rfc822;leviz.kernel.dev@gmail.com> + 99 others); Mon, 17 Apr 2023 02:51:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44394 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230257AbjDQGve (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Mon, 17 Apr 2023 02:51:34 -0400 Received: from mail-sh.amlogic.com (mail-sh.amlogic.com [58.32.228.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AD3C51BB; Sun, 16 Apr 2023 23:50:44 -0700 (PDT) Received: from droid06.amlogic.com (10.18.11.248) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.2507.13; Mon, 17 Apr 2023 14:52:00 +0800 From: Yu Tu <yu.tu@amlogic.com> To: <linux-clk@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-amlogic@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>, Rob Herring <robh+dt@kernel.org>, "Neil Armstrong" <neil.armstrong@linaro.org>, Jerome Brunet <jbrunet@baylibre.com>, Kevin Hilman <khilman@baylibre.com>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>, Martin Blumenstingl <martin.blumenstingl@googlemail.com> CC: <kelvin.zhang@amlogic.com>, <qi.duan@amlogic.com>, Yu Tu <yu.tu@amlogic.com> Subject: [PATCH V7 0/4] Add S4 SoC PLL and Peripheral clock controller Date: Mon, 17 Apr 2023 14:50:01 +0800 Message-ID: <20230417065005.24967-1-yu.tu@amlogic.com> X-Mailer: git-send-email 2.33.1 MIME-Version: 1.0 Content-Transfer-Encoding: 7BIT Content-Type: text/plain; charset=US-ASCII X-Originating-IP: [10.18.11.248] X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763405297527184927?= X-GMAIL-MSGID: =?utf-8?q?1763405297527184927?= |
Series |
Add S4 SoC PLL and Peripheral clock controller
|
|
Message
Yu Tu
April 17, 2023, 6:50 a.m. UTC
1. Add S4 SoC PLL and Peripheral clock controller dt-bindings. 2. Add PLL and Peripheral clock controller driver for S4 SOC. Yu Tu (4): dt-bindings: clock: document Amlogic S4 SoC PLL clock controller dt-bindings: clock: document Amlogic S4 SoC peripherals clock controller clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver clk: meson: s4: add support for Amlogic S4 SoC peripheral clock controller V6 -> V7: Change send patch series as well change format and clock flags suggested by Jerome. Change dt-bindings suggested by Krzysztof. V5 -> V6: Change send patch series, as well change format and clock flags. V4 -> V5: change format and clock flags and adjust the patch series as suggested by Jerome. V3 -> V4: change format and clock flags. V2 -> V3: Use two clock controller. V1 -> V2: Change format as discussed in the email. Link:https://lore.kernel.org/all/20230116074214.2326-1-yu.tu@amlogic.com/ .../clock/amlogic,s4-peripherals-clkc.yaml | 97 + .../bindings/clock/amlogic,s4-pll-clkc.yaml | 50 + MAINTAINERS | 1 + drivers/clk/meson/Kconfig | 25 + drivers/clk/meson/Makefile | 2 + drivers/clk/meson/s4-peripherals.c | 3814 +++++++++++++++++ drivers/clk/meson/s4-peripherals.h | 217 + drivers/clk/meson/s4-pll.c | 902 ++++ drivers/clk/meson/s4-pll.h | 87 + .../clock/amlogic,s4-peripherals-clkc.h | 131 + .../dt-bindings/clock/amlogic,s4-pll-clkc.h | 30 + 11 files changed, 5356 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,s4-peripherals-clkc.yaml create mode 100644 Documentation/devicetree/bindings/clock/amlogic,s4-pll-clkc.yaml create mode 100644 drivers/clk/meson/s4-peripherals.c create mode 100644 drivers/clk/meson/s4-peripherals.h create mode 100644 drivers/clk/meson/s4-pll.c create mode 100644 drivers/clk/meson/s4-pll.h create mode 100644 include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h create mode 100644 include/dt-bindings/clock/amlogic,s4-pll-clkc.h base-commit: 5883d6b83cb0c84c8bc86bd1ff937ea313eb7325
Comments
Hello, On Mon, Apr 17, 2023 at 8:50 AM Yu Tu <yu.tu@amlogic.com> wrote: > > 1. Add S4 SoC PLL and Peripheral clock controller dt-bindings. > 2. Add PLL and Peripheral clock controller driver for S4 SOC. > > Yu Tu (4): > dt-bindings: clock: document Amlogic S4 SoC PLL clock controller > dt-bindings: clock: document Amlogic S4 SoC peripherals clock > controller > clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver > clk: meson: s4: add support for Amlogic S4 SoC peripheral clock > controller > > V6 -> V7: Change send patch series as well change format and clock flags > suggested by Jerome. Change dt-bindings suggested by Krzysztof. Jerome currently has very limited time so I'll be trying to continue with the code-review. Unfortunately I am running out of time for today, so please give me a few more days to review your patches. Thanks four your patience! Best regards, Martin