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[83.9.29.144]) by smtp.gmail.com with ESMTPSA id q17-20020a19a411000000b004d86808fd33sm2365895lfc.15.2023.04.18.05.10.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 05:10:57 -0700 (PDT) From: Konrad Dybcio Subject: [PATCH v2 0/5] MDSS reg bus interconnect Date: Tue, 18 Apr 2023 14:10:55 +0200 Message-Id: <20230417-topic-dpu_regbus-v2-0-91a66d04898e@linaro.org> MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAM+IPmQC/32NQQqDMBAAvyJ7bkoSrWJP/UeRksRVFyQJG5UW8 e9NfUCPMzDMDgmZMMG92IFxo0TBZ9CXAtxk/IiC+sygpS5lpRqxhEhO9HF9MY52TcJY11amaWR 705AzaxIKy8a7KYd+necsI+NA7/Pz7DJPlJbAn3O7qZ/9c9iUkELWg+2dqqvSycdM3nC4Bh6hO 47jC+z6B/rGAAAA To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1681819856; l=1588; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=9T+oPpgA4/nGeRlxxYT3UQzjlTmn8RNRP+pFgS35nLA=; b=XjbFOQMabHazQLE042ggp/Qsi6Htq0N/t8+YpKAeT+K76r5ZaYtdmBUHabs5aYEel2Pn+xJfsea8 xG5lbEfjCv97dAhRoRjnauhXPCsCcfnkcYAN63wmEQL6lNH9N9D7 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763516313953286296?= X-GMAIL-MSGID: =?utf-8?q?1763516313953286296?= v1 -> v2: - Fix "Mbps" -> "MBps" [5/5] - Add an interconnects: entry in dt-bindings (and not only -names..) [1/5] v1: https://lore.kernel.org/r/20230417-topic-dpu_regbus-v1-0-06fbdc1643c0@linaro.org Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's another path that needs to be handled to ensure MDSS functions properly, namely the "reg bus", a.k.a the CPU-MDSS interconnect. Gating that path may have a variety of effects.. from none to otherwise inexplicable DSI timeouts.. This series tries to address the lack of that. Example path: interconnects = <&bimc MASTER_AMPSS_M0 0 &config_noc SLAVE_DISPLAY_CFG 0>; Signed-off-by: Konrad Dybcio --- Konrad Dybcio (5): dt-bindings: display/msm: Add reg bus interconnect drm/msm/dpu1: Rename path references to mdp_path drm/msm/mdss: Rename path references to mdp_path drm/msm/mdss: Handle the reg bus ICC path drm/msm/dpu1: Handle the reg bus ICC path .../bindings/display/msm/mdss-common.yaml | 2 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 10 +++---- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 34 ++++++++++++++++----- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 5 ++-- drivers/gpu/drm/msm/msm_mdss.c | 35 ++++++++++++++-------- 5 files changed, 58 insertions(+), 28 deletions(-) --- base-commit: 4aa1da8d99724f6c0b762b58a71cee7c5e2e109b change-id: 20230417-topic-dpu_regbus-abc94a770952 Best regards,