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[83.9.30.99]) by smtp.gmail.com with ESMTPSA id b16-20020ac25e90000000b004ec8a3d4200sm2053439lfq.293.2023.04.17.08.30.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Apr 2023 08:30:23 -0700 (PDT) From: Konrad Dybcio Subject: [PATCH 0/5] MDSS reg bus interconnect Date: Mon, 17 Apr 2023 17:30:14 +0200 Message-Id: <20230417-topic-dpu_regbus-v1-0-06fbdc1643c0@linaro.org> MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAAZmPWQC/x2N0QrCMAwAf2Xk2UBXJ2X+ioikXdwCoyvNKsLYv xt8vIPjDlCuwgr37oDKH1HZskF/6SAtlGdGmYzBO391Qx9w34oknEp7VZ5jU6SYxoFCcOPNg2W RlDFWymmxMLd1NVkqv+X7/zye5/kDpOQGPncAAAA= To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1681745422; l=1380; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=mhnjPjgyrCcQ+i64OauymCa5KF6SxBBllHrPHpBzDLw=; b=rVoFconVuc2rDcbx8eq5loFRaR3/QTMtcZJG3qdonQSsYSSfI9Zm2BlCKuTX3bLj+F0sVdSRTQrI DiBtMEIeCTeakogOWO44Fj4ndiSLXqFqMmI9zCOgWfQXym7j7e7n X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763439603925786727?= X-GMAIL-MSGID: =?utf-8?q?1763439603925786727?= Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's another path that needs to be handled to ensure MDSS functions properly, namely the "reg bus", a.k.a the CPU-MDSS interconnect. Gating that path may have a variety of effects.. from none to otherwise inexplicable DSI timeouts.. This series tries to address the lack of that. Example path: interconnects = <&bimc MASTER_AMPSS_M0 0 &config_noc SLAVE_DISPLAY_CFG 0>; Signed-off-by: Konrad Dybcio --- Konrad Dybcio (5): dt-bindings: display/msm: Add reg bus interconnect drm/msm/dpu1: Rename path references to mdp_path drm/msm/mdss: Rename path references to mdp_path drm/msm/mdss: Handle the reg bus ICC path drm/msm/dpu1: Handle the reg bus ICC path .../bindings/display/msm/mdss-common.yaml | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 10 +++---- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 34 ++++++++++++++++----- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 5 ++-- drivers/gpu/drm/msm/msm_mdss.c | 35 ++++++++++++++-------- 5 files changed, 57 insertions(+), 28 deletions(-) --- base-commit: d3f2cd24819158bb70701c3549e586f9df9cee67 change-id: 20230417-topic-dpu_regbus-abc94a770952 Best regards,