mbox series

[0/3] cacheinfo: Correctly fallback to using clidr_el1's information

Message ID 20230327115953.788244-1-pierre.gondois@arm.com
Headers
Series cacheinfo: Correctly fallback to using clidr_el1's information |

Message

Pierre Gondois March 27, 2023, 11:59 a.m. UTC 
  The cache information can be extracted from either a Device
Tree (DT), the PPTT ACPI table, or arch registers (clidr_el1
for arm64).

When the DT is used but no cache properties are advertised,
the current code doesn't correctly fallback to using arch information.

Correct this. Also use the assumption that L1 data/instruction caches
are private and L2/higher caches are shared when the cache information
is coming form clidr_el1.

Pierre Gondois (3):
  cacheinfo: Check sib_leaf in cache_leaves_are_shared()
  cacheinfo: Check cache properties are present in DT
  cacheinfo: Add use_arch[|_cache]_info field/function

 arch/arm64/kernel/cacheinfo.c |  5 ++++
 drivers/base/cacheinfo.c      | 53 ++++++++++++++++++++++++++++++++---
 include/linux/cacheinfo.h     |  2 ++
 3 files changed, 56 insertions(+), 4 deletions(-)