Message ID | 20230321111958.2800005-1-s-vadapalli@ti.com |
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[2620:137:e000::1:20]) by mx.google.com with ESMTP id 4-20020a630004000000b005030a59a80bsi13594111pga.178.2023.03.21.04.28.47; Tue, 21 Mar 2023 04:29:02 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=uRgn9Zom; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231136AbjCULUo (ORCPT <rfc822;ezelljr.billy@gmail.com> + 99 others); Tue, 21 Mar 2023 07:20:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39672 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229671AbjCULUm (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Tue, 21 Mar 2023 07:20:42 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DE8EA2F7AC; Tue, 21 Mar 2023 04:20:23 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 32LBK3ql127836; Tue, 21 Mar 2023 06:20:03 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1679397603; bh=nBzsrK9F0f/kSP64wqEA7pCc1XDfaG2toYVJJNk9SuI=; h=From:To:CC:Subject:Date; b=uRgn9ZomS8XS+g4sI+2kHGYnwdniso1bP4nCcpIB3RrCx4rH2TOiIH3tTqM9M5FD6 ty3F6dp+XjcL/qtuPNzogEFaBiWAegy9JHT94Aa+gtBRwRWK7lMw6PpMKQigO6uKuI hEVq8qv891a8FO9HhenYXwdk7OCCIhiqgiqzZT8E= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 32LBK3PQ008204 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 21 Mar 2023 06:20:03 -0500 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Tue, 21 Mar 2023 06:20:02 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Tue, 21 Mar 2023 06:20:02 -0500 Received: from uda0492258.dhcp.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 32LBJxVm088542; Tue, 21 Mar 2023 06:20:00 -0500 From: Siddharth Vadapalli <s-vadapalli@ti.com> To: <davem@davemloft.net>, <edumazet@google.com>, <kuba@kernel.org>, <linux@armlinux.org.uk>, <pabeni@redhat.com>, <rogerq@kernel.org> CC: <netdev@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <srk@ti.com>, <s-vadapalli@ti.com> Subject: [PATCH net-next 0/4] Add CPSWxG SGMII support for J7200 and J721E Date: Tue, 21 Mar 2023 16:49:54 +0530 Message-ID: <20230321111958.2800005-1-s-vadapalli@ti.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1760976586734590986?= X-GMAIL-MSGID: =?utf-8?q?1760976586734590986?= |
Series |
Add CPSWxG SGMII support for J7200 and J721E
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Message
Siddharth Vadapalli
March 21, 2023, 11:19 a.m. UTC
Hello, This series adds support to configure the CPSW Ethernet Switch in SGMII mode, using the am65-cpsw-nuss driver. SGMII mode is supported by the CPSWxG instances on TI's J7200 and J721E SoCs. Thus, SGMII mode is added in the list of extra_modes for the appropriate compatibles corresponding to the aforementioned SoCs. Additionally, the method of setting the supported interface via struct "phylink_config" is simplified by converting the IF/ELSE statements to SWITCH statements. Regards, Siddharth. Siddharth Vadapalli (4): net: ethernet: ti: am65-cpsw: Simplify setting supported interface net: ethernet: ti: am65-cpsw: Add support for SGMII mode net: ethernet: ti: am65-cpsw: Enable SGMII mode for J7200 net: ethernet: ti: am65-cpsw: Enable SGMII mode for J721E drivers/net/ethernet/ti/am65-cpsw-nuss.c | 42 +++++++++++++++++++----- 1 file changed, 33 insertions(+), 9 deletions(-)
Comments
On Tue, Mar 21, 2023 at 04:49:56PM +0530, Siddharth Vadapalli wrote: > Add support for configuring the CPSW Ethernet Switch in SGMII mode. > > Depending on the SoC, allow selecting SGMII mode as a supported interface, > based on the compatible used. > > Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> > --- > drivers/net/ethernet/ti/am65-cpsw-nuss.c | 11 ++++++++++- > 1 file changed, 10 insertions(+), 1 deletion(-) > > diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c > index cba8db14e160..d2ca1f2035f4 100644 > --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c > +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c > @@ -76,6 +76,7 @@ > #define AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 0x31C > > #define AM65_CPSW_SGMII_CONTROL_REG 0x010 > +#define AM65_CPSW_SGMII_MR_ADV_ABILITY_REG 0x018 > #define AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE BIT(0) Isn't this misplaced? Shouldn't AM65_CPSW_SGMII_MR_ADV_ABILITY_REG come after AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE, rather than splitting that from its register offset definition? If the advertisement register is at 0x18, and the lower 16 bits is the advertisement, are the link partner advertisement found in the upper 16 bits? > #define AM65_CPSW_CTL_VLAN_AWARE BIT(1) > @@ -1496,9 +1497,14 @@ static void am65_cpsw_nuss_mac_config(struct phylink_config *config, unsigned in > struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); > struct am65_cpsw_common *common = port->common; > > - if (common->pdata.extra_modes & BIT(state->interface)) > + if (common->pdata.extra_modes & BIT(state->interface)) { > + if (state->interface == PHY_INTERFACE_MODE_SGMII) > + writel(ADVERTISE_SGMII, > + port->sgmii_base + AM65_CPSW_SGMII_MR_ADV_ABILITY_REG); > + I think we can do better with this, by implementing proper PCS support. It seems manufacturers tend to use bought-in IP for this, so have a look at drivers/net/pcs/ to see whether any of those (or the one in the Mediatek patch set on netdev that has recently been applied) will idrive your hardware. However, given the definition of AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE, I suspect you won't find a compatible implementation. Thanks.
Hello: This series was applied to netdev/net-next.git (main) by Jakub Kicinski <kuba@kernel.org>: On Tue, 21 Mar 2023 16:49:54 +0530 you wrote: > Hello, > > This series adds support to configure the CPSW Ethernet Switch in SGMII > mode, using the am65-cpsw-nuss driver. SGMII mode is supported by the > CPSWxG instances on TI's J7200 and J721E SoCs. Thus, SGMII mode is added > in the list of extra_modes for the appropriate compatibles corresponding > to the aforementioned SoCs. > > [...] Here is the summary with links: - [net-next,1/4] net: ethernet: ti: am65-cpsw: Simplify setting supported interface https://git.kernel.org/netdev/net-next/c/a2935a1cd85f - [net-next,2/4] net: ethernet: ti: am65-cpsw: Add support for SGMII mode https://git.kernel.org/netdev/net-next/c/e0f72db37547 - [net-next,3/4] net: ethernet: ti: am65-cpsw: Enable SGMII mode for J7200 https://git.kernel.org/netdev/net-next/c/2e20e764f24e - [net-next,4/4] net: ethernet: ti: am65-cpsw: Enable SGMII mode for J721E https://git.kernel.org/netdev/net-next/c/186016da9cca You are awesome, thank you!