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[92.145.124.62]) by smtp.gmail.com with ESMTPSA id r7-20020a0560001b8700b002c7163660a9sm1646775wru.105.2023.03.10.01.45.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Mar 2023 01:45:44 -0800 (PST) From: Alexandre Ghiti To: Catalin Marinas , Will Deacon , Paul Walmsley , Palmer Dabbelt , Albert Ou , Rob Herring , Frank Rowand , Mike Rapoport , Andrew Morton , Anup Patel , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-mm@kvack.org Cc: Alexandre Ghiti Subject: [PATCH v7 0/4] riscv: Use PUD/P4D/PGD pages for the linear mapping Date: Fri, 10 Mar 2023 10:45:35 +0100 Message-Id: <20230310094539.764357-1-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759974346784561954?= X-GMAIL-MSGID: =?utf-8?q?1759974928082790256?= This patchset intends to improve tlb utilization by using hugepages for the linear mapping. As reported by Anup in v6, when STRICT_KERNEL_RWX is enabled, we must take care of isolating the kernel text and rodata so that they are not mapped with a PUD mapping which would then assign wrong permissions to the whole region: it is achieved by introducing a new memblock API. Another patch makes use of this new API in arm64 which used some sort of hack to solve this issue: it was built/boot tested successfully. base-commit-tag: v6.3-rc1 v7: - Fix Anup bug report by introducing memblock_isolate_memory which allows us to split the memblock mappings and then avoid to map the the PUD which contains the kernel as read only - Add a patch to arm64 to use this newly introduced API v6: - quiet LLVM warning by casting phys_ram_base into an unsigned long v5: - Fix nommu builds by getting rid of riscv_pfn_base in patch 1, thanks Conor - Add RB from Andrew v4: - Rebase on top of v6.2-rc3, as noted by Conor - Add Acked-by Rob v3: - Change the comment about initrd_start VA conversion so that it fits ARM64 and RISCV64 (and others in the future if needed), as suggested by Rob v2: - Add a comment on why RISCV64 does not need to set initrd_start/end that early in the boot process, as asked by Rob Alexandre Ghiti (4): riscv: Get rid of riscv_pfn_base variable mm: Introduce memblock_isolate_memory arm64: Make use of memblock_isolate_memory for the linear mapping riscv: Use PUD/P4D/PGD pages for the linear mapping arch/arm64/mm/mmu.c | 4 ++-- arch/riscv/include/asm/page.h | 19 +++++++++++++++-- arch/riscv/mm/init.c | 39 ++++++++++++++++++++++++++--------- arch/riscv/mm/physaddr.c | 16 ++++++++++++++ drivers/of/fdt.c | 11 +++++----- include/linux/memblock.h | 1 + mm/memblock.c | 22 +++++++++++++++++++- 7 files changed, 92 insertions(+), 20 deletions(-) Reviewed-by: Anup Patel Tested-by: Anup Patel