mbox series

[RFC,v2,0/7] Add dedicated Qcom ICE driver

Message ID 20230308155838.1094920-1-abel.vesa@linaro.org
Headers
Series Add dedicated Qcom ICE driver |

Message

Abel Vesa March 8, 2023, 3:58 p.m. UTC 
  As both SDCC and UFS drivers use the ICE with duplicated implementation,
while none of the currently supported platforms make use concomitantly
of the same ICE IP block instance, the new SM8550 allows both UFS and
SDCC to do so. In order to support such scenario, there is a need for
a unified implementation and a devicetree node to be shared between
both types of storage devices. So lets drop the duplicate implementation
of the ICE from both SDCC and UFS and make it a dedicated (soc) driver.
Also, switch all UFS and SDCC devicetree nodes to use the new ICE
approach.

See each individual patch for changelogs.

The v1 is here:
https://lore.kernel.org/all/20230214120253.1098426-1-abel.vesa@linaro.org/

Abel Vesa (7):
  dt-bindings: soc: qcom: Add schema for Inline Crypto Engine
  dt-bindings: ufs: qcom: Add ICE phandle and drop core clock
  dt-bindings: mmc: sdhci-msm: Add ICE phandle and drop core clock
  soc: qcom: Make the Qualcomm UFS/SDCC ICE a dedicated driver
  scsi: ufs: ufs-qcom: Switch to the new ICE API
  mmc: sdhci-msm: Switch to the new ICE API
  arm64: dts: qcom: Add the Inline Crypto Engine nodes

 .../devicetree/bindings/mmc/sdhci-msm.yaml    |   9 +-
 .../soc/qcom/qcom,inline-crypto-engine.yaml   |  42 +++
 .../devicetree/bindings/ufs/qcom,ufs.yaml     |  14 +-
 arch/arm64/boot/dts/qcom/sdm630.dtsi          |  18 +-
 arch/arm64/boot/dts/qcom/sdm670.dtsi          |  15 +-
 arch/arm64/boot/dts/qcom/sdm845.dtsi          |  21 +-
 arch/arm64/boot/dts/qcom/sm6115.dtsi          |  37 ++-
 arch/arm64/boot/dts/qcom/sm6350.dtsi          |  31 +-
 arch/arm64/boot/dts/qcom/sm8150.dtsi          |  21 +-
 arch/arm64/boot/dts/qcom/sm8450.dtsi          |  22 +-
 drivers/mmc/host/Kconfig                      |   2 +-
 drivers/mmc/host/sdhci-msm.c                  | 257 ++-------------
 drivers/soc/qcom/Kconfig                      |   6 +
 drivers/soc/qcom/Makefile                     |   1 +
 drivers/soc/qcom/ice.c                        | 301 ++++++++++++++++++
 drivers/ufs/host/Kconfig                      |   2 +-
 drivers/ufs/host/Makefile                     |   1 -
 drivers/ufs/host/ufs-qcom-ice.c               | 244 --------------
 drivers/ufs/host/ufs-qcom.c                   |  50 ++-
 drivers/ufs/host/ufs-qcom.h                   |  30 +-
 include/soc/qcom/ice.h                        |  65 ++++
 21 files changed, 608 insertions(+), 581 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,inline-crypto-engine.yaml
 create mode 100644 drivers/soc/qcom/ice.c
 delete mode 100644 drivers/ufs/host/ufs-qcom-ice.c
 create mode 100644 include/soc/qcom/ice.h

Comments

Eric Biggers March 8, 2023, 8:03 p.m. UTC | #1 
Hi Abel,

On Wed, Mar 08, 2023 at 05:58:31PM +0200, Abel Vesa wrote:
> As both SDCC and UFS drivers use the ICE with duplicated implementation,
> while none of the currently supported platforms make use concomitantly
> of the same ICE IP block instance, the new SM8550 allows both UFS and
> SDCC to do so. In order to support such scenario, there is a need for
> a unified implementation and a devicetree node to be shared between
> both types of storage devices. So lets drop the duplicate implementation
> of the ICE from both SDCC and UFS and make it a dedicated (soc) driver.
> Also, switch all UFS and SDCC devicetree nodes to use the new ICE
> approach.
> 
> See each individual patch for changelogs.
> 
> The v1 is here:
> https://lore.kernel.org/all/20230214120253.1098426-1-abel.vesa@linaro.org/
> 
> Abel Vesa (7):
>   dt-bindings: soc: qcom: Add schema for Inline Crypto Engine
>   dt-bindings: ufs: qcom: Add ICE phandle and drop core clock
>   dt-bindings: mmc: sdhci-msm: Add ICE phandle and drop core clock
>   soc: qcom: Make the Qualcomm UFS/SDCC ICE a dedicated driver
>   scsi: ufs: ufs-qcom: Switch to the new ICE API
>   mmc: sdhci-msm: Switch to the new ICE API
>   arm64: dts: qcom: Add the Inline Crypto Engine nodes

Does this address all the comments on v1?  I had also asked some questions on
v1.  It would be helpful if you would respond.

- Eric
Abel Vesa March 8, 2023, 9:55 p.m. UTC | #2 
On 23-03-08 12:03:17, Eric Biggers wrote:
> Hi Abel,
> 
> On Wed, Mar 08, 2023 at 05:58:31PM +0200, Abel Vesa wrote:
> > As both SDCC and UFS drivers use the ICE with duplicated implementation,
> > while none of the currently supported platforms make use concomitantly
> > of the same ICE IP block instance, the new SM8550 allows both UFS and
> > SDCC to do so. In order to support such scenario, there is a need for
> > a unified implementation and a devicetree node to be shared between
> > both types of storage devices. So lets drop the duplicate implementation
> > of the ICE from both SDCC and UFS and make it a dedicated (soc) driver.
> > Also, switch all UFS and SDCC devicetree nodes to use the new ICE
> > approach.
> > 
> > See each individual patch for changelogs.
> > 
> > The v1 is here:
> > https://lore.kernel.org/all/20230214120253.1098426-1-abel.vesa@linaro.org/
> > 
> > Abel Vesa (7):
> >   dt-bindings: soc: qcom: Add schema for Inline Crypto Engine
> >   dt-bindings: ufs: qcom: Add ICE phandle and drop core clock
> >   dt-bindings: mmc: sdhci-msm: Add ICE phandle and drop core clock
> >   soc: qcom: Make the Qualcomm UFS/SDCC ICE a dedicated driver
> >   scsi: ufs: ufs-qcom: Switch to the new ICE API
> >   mmc: sdhci-msm: Switch to the new ICE API
> >   arm64: dts: qcom: Add the Inline Crypto Engine nodes
> 
> Does this address all the comments on v1?  I had also asked some questions on
> v1.  It would be helpful if you would respond.

Sorry about not doing that earlier. Did that now.

> 
> - Eric