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[2620:137:e000::1:20]) by mx.google.com with ESMTP id z190-20020a6233c7000000b005a8c6715004si2049047pfz.86.2023.03.03.04.52.18; Fri, 03 Mar 2023 04:52:32 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linux.dev header.s=key1 header.b=aPwRRuPx; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linux.dev Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229618AbjCCMq4 (ORCPT <rfc822;davidbtadokoro@gmail.com> + 99 others); Fri, 3 Mar 2023 07:46:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58434 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230053AbjCCMqz (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Fri, 3 Mar 2023 07:46:55 -0500 Received: from out-59.mta1.migadu.com (out-59.mta1.migadu.com [IPv6:2001:41d0:203:375::3b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 210AE199CD for <linux-kernel@vger.kernel.org>; Fri, 3 Mar 2023 04:46:54 -0800 (PST) X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1677847610; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=M6pZyT/67NWijZcPpIJ5sKmOZPf0rH1QPbb9QcorFOc=; b=aPwRRuPxNWGO4HrjpTemwHdCqLgl5zvBqeXarmoMg9ldY+VKCM7cFGugnAkPlUpefqj/2R sXWWPqiSAbZBee3Zi6AS/+A7qcKEkX71oahK8A1ZBe4oB3D0//wB1V0f8/dU1LgROp0Odx Somi49PJ1rgoHIVt21Ymi03ruD+FMhw= From: Cai Huoqing <cai.huoqing@linux.dev> To: fancer.lancer@gmail.com Cc: Cai Huoqing <cai.huoqing@linux.dev>, Gustavo Pimentel <gustavo.pimentel@synopsys.com>, Vinod Koul <vkoul@kernel.org>, Jingoo Han <jingoohan1@gmail.com>, Lorenzo Pieralisi <lpieralisi@kernel.org>, =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= <kw@linux.com>, Rob Herring <robh@kernel.org>, Bjorn Helgaas <bhelgaas@google.com>, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v5 0/4] dmaengine: dw-edma: Add support for native HDMA Date: Fri, 3 Mar 2023 20:46:30 +0800 Message-Id: <20230303124642.5519-1-cai.huoqing@linux.dev> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Migadu-Flow: FLOW_OUT X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759351095009346620?= X-GMAIL-MSGID: =?utf-8?q?1759351095009346620?= |
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dmaengine: dw-edma: Add support for native HDMA
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Message
Cai Huoqing
March 3, 2023, 12:46 p.m. UTC
Add support for HDMA NATIVE, as long the IP design has set the compatible register map parameter-HDMA_NATIVE, which allows compatibility for native HDMA register configuration. The HDMA Hyper-DMA IP is an enhancement of the eDMA embedded-DMA IP. And the native HDMA registers are different from eDMA, so this patch add support for HDMA NATIVE mode. HDMA write and read channels operate independently to maximize the performance of the HDMA read and write data transfer over the link When you configure the HDMA with multiple read channels, then it uses a round robin (RR) arbitration scheme to select the next read channel to be serviced.The same applies when youhave multiple write channels. The native HDMA driver also supports a maximum of 16 independent channels (8 write + 8 read), which can run simultaneously. Both SAR (Source Address Register) and DAR (Destination Address Register) are aligned to byte. Cai huoqing (4): dmaengine: dw-edma: Rename dw_edma_core_ops structure to dw_edma_plat_ops dmaengine: dw-edma: Create a new dw_edma_core_ops structure to abstract controller operation dmaengine: dw-edma: Add support for native HDMA dmaengine: dw-edma: Add HDMA DebugFS support v4->v5: [1/4] 1.Revert the instance dw_edma_pcie_core_ops 2.Move the change EDMA_MF_HDMA_NATIVE to patch[3/4] [2/4] 3.Refactor add return irqreturn_t to dw_edma_core_handle_int 4.Define dw_edma_core_handle_int as inline fuction and move to dw-edma-core.h. [3/4] 5.Add missing the function call -dw_hdma_v0_core_register. [4/4] 6.Remove the check of *regs_dent *ch_dent. v4 link: https://lore.kernel.org/lkml/Y%2F62%2FXUiHz363qmD@chq-MS-7D45/ drivers/dma/dw-edma/Makefile | 8 +- drivers/dma/dw-edma/dw-edma-core.c | 87 ++---- drivers/dma/dw-edma/dw-edma-core.h | 64 ++++ drivers/dma/dw-edma/dw-edma-pcie.c | 2 +- drivers/dma/dw-edma/dw-edma-v0-core.c | 75 ++++- drivers/dma/dw-edma/dw-edma-v0-core.h | 14 +- drivers/dma/dw-edma/dw-hdma-v0-core.c | 304 +++++++++++++++++++ drivers/dma/dw-edma/dw-hdma-v0-core.h | 17 ++ drivers/dma/dw-edma/dw-hdma-v0-debugfs.c | 175 +++++++++++ drivers/dma/dw-edma/dw-hdma-v0-debugfs.h | 22 ++ drivers/dma/dw-edma/dw-hdma-v0-regs.h | 129 ++++++++ drivers/pci/controller/dwc/pcie-designware.c | 2 +- include/linux/dma/edma.h | 7 +- 13 files changed, 815 insertions(+), 91 deletions(-) create mode 100644 drivers/dma/dw-edma/dw-hdma-v0-core.c create mode 100644 drivers/dma/dw-edma/dw-hdma-v0-core.h create mode 100644 drivers/dma/dw-edma/dw-hdma-v0-debugfs.c create mode 100644 drivers/dma/dw-edma/dw-hdma-v0-debugfs.h create mode 100644 drivers/dma/dw-edma/dw-hdma-v0-regs.h