mbox series

[v3,0/8] Add Array BIST test support to IFS

Message ID 20230301015942.462799-1-jithu.joseph@intel.com
Headers
Series Add Array BIST test support to IFS |

Message

Jithu Joseph March 1, 2023, 1:59 a.m. UTC 
  Changes in v3
 - GregKH 
    -  Separating read-only fields from rw fields in
       struct ifs_device (patch 1/8)
    -  Remove the subdirectory intel_ifs/<n> for devicenode (patch 2/8)
    -  Replaced an enum with #define (patch 4/8)
 - Dave Hansen
    - Remove tracing patch
    - ifs_array_test_core() (patch 6/8)
        - fix an initialization bug
        - other suggested changes
    - Use basic types in ifs_array for first two fields. (kept
      the union to avoid type castings)

v2 submission:
Link: https://lore.kernel.org/lkml/20230214234426.344960-1-jithu.joseph@intel.com/

Changes in v2
 - remove duplicate initializations from ifs_array_test_core()
   (Dave Hansen, patch 4/7)
 - remove bit parsing from tracing fast path to tracing 
   output (Steven Rostedt, patch 5/7)
 - move "ATTRIBUTE_GROUPS(plat_ifs_array)" to core.c and remove
   exporting function ifs_get_array_groups() (Greg KH, patch 3/7)
 - Generalized doc and ABI doc (Greg KH, patches 6/7 and 7/7)

v1 submission:
Link: https://lore.kernel.org/lkml/20230131234302.3997223-1-jithu.joseph@intel.com/

Array BIST is a new type of core test introduced under the Intel Infield
Scan (IFS) suite of tests.

Emerald Rapids (EMR) is the first CPU to support Array BIST.
Array BIST performs tests on some portions of the core logic such as
caches and register files. These are different portions of the silicon
compared to the parts tested by Scan at Field (SAF).

Unlike SAF, Array BIST doesn't require any test content to be loaded.

Jithu Joseph (8):
  platform/x86/intel/ifs: Reorganize driver data
  platform/x86/intel/ifs: IFS cleanup
  x86/include/asm/msr-index.h: Add IFS Array test bits
  platform/x86/intel/ifs: Introduce Array Scan test to IFS
  platform/x86/intel/ifs: Sysfs interface for Array BIST
  platform/x86/intel/ifs: Implement Array BIST test
  platform/x86/intel/ifs: Update IFS doc
  Documentation/ABI: Update IFS ABI doc

 arch/x86/include/asm/msr-index.h              |  2 +
 drivers/platform/x86/intel/ifs/ifs.h          | 62 +++++++++----
 drivers/platform/x86/intel/ifs/core.c         | 92 ++++++++++++++-----
 drivers/platform/x86/intel/ifs/load.c         |  8 +-
 drivers/platform/x86/intel/ifs/runtest.c      | 91 +++++++++++++++++-
 drivers/platform/x86/intel/ifs/sysfs.c        | 17 ++--
 .../ABI/testing/sysfs-platform-intel-ifs      |  8 +-
 7 files changed, 221 insertions(+), 59 deletions(-)

Comments

Hans de Goede March 7, 2023, 11:02 a.m. UTC | #1 
Hi Jithu,

On 3/1/23 02:59, Jithu Joseph wrote:
> Changes in v3
>  - GregKH 
>     -  Separating read-only fields from rw fields in
>        struct ifs_device (patch 1/8)
>     -  Remove the subdirectory intel_ifs/<n> for devicenode (patch 2/8)
>     -  Replaced an enum with #define (patch 4/8)
>  - Dave Hansen
>     - Remove tracing patch
>     - ifs_array_test_core() (patch 6/8)
>         - fix an initialization bug
>         - other suggested changes
>     - Use basic types in ifs_array for first two fields. (kept
>       the union to avoid type castings)

Thank you for the new version. Given all the feedback on
the previous 2 versions I'm going to wait a bit to see if more
feedback comes in before reviewing this myself.

Regards,

Hans




> v2 submission:
> Link: https://lore.kernel.org/lkml/20230214234426.344960-1-jithu.joseph@intel.com/
> 
> Changes in v2
>  - remove duplicate initializations from ifs_array_test_core()
>    (Dave Hansen, patch 4/7)
>  - remove bit parsing from tracing fast path to tracing 
>    output (Steven Rostedt, patch 5/7)
>  - move "ATTRIBUTE_GROUPS(plat_ifs_array)" to core.c and remove
>    exporting function ifs_get_array_groups() (Greg KH, patch 3/7)
>  - Generalized doc and ABI doc (Greg KH, patches 6/7 and 7/7)
> 
> v1 submission:
> Link: https://lore.kernel.org/lkml/20230131234302.3997223-1-jithu.joseph@intel.com/
> 
> Array BIST is a new type of core test introduced under the Intel Infield
> Scan (IFS) suite of tests.
> 
> Emerald Rapids (EMR) is the first CPU to support Array BIST.
> Array BIST performs tests on some portions of the core logic such as
> caches and register files. These are different portions of the silicon
> compared to the parts tested by Scan at Field (SAF).
> 
> Unlike SAF, Array BIST doesn't require any test content to be loaded.
> 
> Jithu Joseph (8):
>   platform/x86/intel/ifs: Reorganize driver data
>   platform/x86/intel/ifs: IFS cleanup
>   x86/include/asm/msr-index.h: Add IFS Array test bits
>   platform/x86/intel/ifs: Introduce Array Scan test to IFS
>   platform/x86/intel/ifs: Sysfs interface for Array BIST
>   platform/x86/intel/ifs: Implement Array BIST test
>   platform/x86/intel/ifs: Update IFS doc
>   Documentation/ABI: Update IFS ABI doc
> 
>  arch/x86/include/asm/msr-index.h              |  2 +
>  drivers/platform/x86/intel/ifs/ifs.h          | 62 +++++++++----
>  drivers/platform/x86/intel/ifs/core.c         | 92 ++++++++++++++-----
>  drivers/platform/x86/intel/ifs/load.c         |  8 +-
>  drivers/platform/x86/intel/ifs/runtest.c      | 91 +++++++++++++++++-
>  drivers/platform/x86/intel/ifs/sysfs.c        | 17 ++--
>  .../ABI/testing/sysfs-platform-intel-ifs      |  8 +-
>  7 files changed, 221 insertions(+), 59 deletions(-)
>