mbox series

[v1,0/3] Add PLL clocks driver for StarFive JH7110

Message ID 20230221141147.303642-1-xingyu.wu@starfivetech.com
Headers
Series Add PLL clocks driver for StarFive JH7110 |

Message

Xingyu Wu Feb. 21, 2023, 2:11 p.m. UTC 
  This patch serises are to add PLL clocks driver and modify
the system clock driver to depend on PLL clocks driver for the 
StarFive JH7110 RISC-V SoC.

PLL are high speed, low jitter frequency synthesizers in JH7110.
Each PLL clocks work in integer mode or fraction mode by some dividers,
and the dividers are set in several syscon registers.
The formula for calculating frequency is: 
Fvco = Fref * (NI + NF) / M / Q1

The first patch adds docunmentation to describe PLL clock bindings,
and the second patch adds driver to support PLL clocks for JH7110 and 
modifies the system clock driver.

This patchset should be applied after this patchset about JH71x0 clock
driver:
https://lore.kernel.org/all/20230221024645.127922-1-hal.feng@starfivetech.com/

Xingyu Wu (3):
  dt-bindings: clock: Add StarFive JH7110 PLL clock generator
  clk: starfive: Add StarFive JH7110 PLL clock driver
  riscv: dts: starfive: jh7110: Add PLL clock node

 .../bindings/clock/starfive,jh7110-pll.yaml   |  45 ++
 arch/riscv/boot/dts/starfive/jh7110.dtsi      |  15 +-
 drivers/clk/starfive/Kconfig                  |   9 +
 drivers/clk/starfive/Makefile                 |   1 +
 .../clk/starfive/clk-starfive-jh7110-pll.c    | 433 ++++++++++++++++++
 .../clk/starfive/clk-starfive-jh7110-pll.h    | 286 ++++++++++++
 .../clk/starfive/clk-starfive-jh7110-sys.c    |  40 +-
 .../dt-bindings/clock/starfive,jh7110-crg.h   |  12 +-
 8 files changed, 807 insertions(+), 34 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml
 create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-pll.c
 create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-pll.h


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