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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Feb 2023 11:17:16.8202 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5bdfcf60-d439-4a7d-7d9c-08db09c60969 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT034.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5092 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757261565292577104?= X-GMAIL-MSGID: =?utf-8?q?1757261565292577104?= Below series [1] attempted to support DT based PCIe wake feature in generic PCI core driver. This series was left at v13 and final comments are not addressed. I am continuing this series from v14 by addressing all comments in v13. I dropped rockchip device tree patch because I don't have hardware to verify it. Instead, I verified these patches on NVIDIA Jetson AGX Orin Developer Kit and included its device tree changes in this series. [1] https://lore.kernel.org/all/20171226023646.17722-1-jeffy.chen@rock-chips.com/ Changes in v14: Updated commit message for DT bindings patch to reflect that DT properties are tied to PCI-PCI Bridge. Addressed review comments on PCI interrupt parsing patch. Dropped rockchip device tree patch. Added Jetson AGX OrinDeveloper Kit device tree and Tegra PMC patches. Changes in v13: Fix compiler error reported by kbuild test robot Changes in v12: Only add irq definitions for PCI devices and rewrite the commit message. Enable the wake irq in noirq stage to avoid possible irq storm. Changes in v11: Address Brian's comments. Only support 1-per-device PCIe WAKE# pin as suggested. Move to pcie port as Brian suggested. Changes in v10: Use device_set_wakeup_capable() instead of device_set_wakeup_enable(), since dedicated wakeirq will be lost in device_set_wakeup_enable(false). Changes in v9: Add section for PCI devices and rewrite the commit message. Fix check error in .cleanup(). Move dedicated wakeirq setup to setup() callback and use device_set_wakeup_enable() to enable/disable. Rewrite the commit message. Changes in v8: Add optional "pci", and rewrite commit message. Add pci-of.c and use platform_pm_ops to handle the PCIe WAKE# signal. Rewrite the commit message. Changes in v7: Move PCIE_WAKE handling into pci core. Changes in v6: Fix device_init_wake error handling, and add some comments. Changes in v5: Move to pci.txt Rebase. Use "wakeup" instead of "wake" Changes in v3: Fix error handling. Changes in v2: Use dev_pm_set_dedicated_wake_irq. Jeffy Chen (3): dt-bindings: PCI: Add definition of PCIe WAKE# irq and PCI irq of/irq: Adjust of_pci_irq parsing for multiple interrupts PCI / PM: Add support for the PCIe WAKE# signal for OF Manikanta Maddireddy (2): arm64: tegra: Add PCIe port node with PCIe WAKE# for C1 controller soc/tegra: pmc: Add Tegra234 PCIe wake event Documentation/devicetree/bindings/pci/pci.txt | 8 +++ .../nvidia/tegra234-p3737-0000+p3701-0000.dts | 11 ++++ drivers/pci/of.c | 63 ++++++++++++++++++- drivers/pci/pci-driver.c | 10 +++ drivers/pci/pci.c | 7 +++ drivers/pci/pci.h | 8 +++ drivers/soc/tegra/pmc.c | 1 + 7 files changed, 105 insertions(+), 3 deletions(-)