mbox series

[v1,0/3] Update SMCA Error Decoding for AMD EPYC Processors

Message ID 20230116191102.4226-1-avadnaik@amd.com
Headers
Series Update SMCA Error Decoding for AMD EPYC Processors |

Message

Naik, Avadhut Jan. 16, 2023, 7:10 p.m. UTC 
  Modern AMD EPYC processors support Scalable MCA (SMCA) Error decoding.
Currently however, on Family 19h and 1Ah based, AMD EPYC processors, not
all SMCA errors are being decoded. This patchset attempts to address the
very issue by updating error description structures and handling errata
of some SMCA bank types.

The first patch adds new error descriptions for various SMCA bank types
while also rewording existing and removing unused error descriptions.

The second patch handles the mismatch, encountered on some AMD CPUs, between
the HWID read from the MCA_IPID register and the HWID expected by the kernel
for XGMI Controller SMCA bank type during SMCA initialization.

The third patch tackles the erratum no. 1384, encountered on Genoa and a
few other CPUs due to bit reassignments in Control register of the Coherent
Slave (CS) SMCA bank type.

Avadhut Naik (2):
  x86/MCE/AMD: Add HWID Fixup for PCS_XGMI SMCA
  x86/MCE/AMD: Handle reassigned bit definitions for CS SMCA

Yazen Ghannam (1):
  EDAC/mce_amd: Update SMCA bank error descriptions

 arch/x86/include/asm/mce.h    |  1 +
 arch/x86/kernel/cpu/mce/amd.c | 50 +++++++++++++++++++++-
 drivers/edac/mce_amd.c        | 79 +++++++++++++++++++++++++----------
 3 files changed, 107 insertions(+), 23 deletions(-)