mbox series

[0/2] Allwinner power domain support

Message ID 20221231160402.16157-1-samuel@sholland.org
Headers
Series Allwinner power domain support |

Message

Samuel Holland Dec. 31, 2022, 4:04 p.m. UTC 
  This series adds support for the power controller found in D1 and other
recent Allwinner SoCs. There is no first-party documentation, but there
are a couple of vendor drivers for different hardware revisions[1][2],
and the register definitions were easy to verify empirically.

I have tested this driver on D1 with the video engine. There is no DT
update patch here to avoid dependencies between series. The example in
the binding is what will go in the D1 DT.

[1]: https://github.com/mangopi-sbc/tina-linux-5.4/blob/main/drivers/soc/sunxi/gpu_domain.c
[1]: https://github.com/mangopi-sbc/tina-linux-5.4/blob/main/drivers/soc/sunxi/pm_domains.c


Samuel Holland (2):
  dt-bindings: power: Add Allwinner D1 PPU
  soc: sunxi: Add Allwinner D1 PPU driver

 .../power/allwinner,sun20i-d1-ppu.yaml        |  54 +++++
 drivers/soc/sunxi/Kconfig                     |   9 +
 drivers/soc/sunxi/Makefile                    |   1 +
 drivers/soc/sunxi/sun20i-ppu.c                | 207 ++++++++++++++++++
 .../power/allwinner,sun20i-d1-ppu.h           |  10 +
 5 files changed, 281 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/power/allwinner,sun20i-d1-ppu.yaml
 create mode 100644 drivers/soc/sunxi/sun20i-ppu.c
 create mode 100644 include/dt-bindings/power/allwinner,sun20i-d1-ppu.h

Comments

Jernej Škrabec Jan. 5, 2023, 4:34 p.m. UTC | #1 
Dne sobota, 31. december 2022 ob 17:04:00 CET je Samuel Holland napisal(a):
> This series adds support for the power controller found in D1 and other
> recent Allwinner SoCs. There is no first-party documentation, but there
> are a couple of vendor drivers for different hardware revisions[1][2],
> and the register definitions were easy to verify empirically.
> 
> I have tested this driver on D1 with the video engine. There is no DT
> update patch here to avoid dependencies between series. The example in
> the binding is what will go in the D1 DT.

So such driver is needed for H616 for GPU? Or is power domain handling 
different there?

Best regards,
Jernej

> 
> [1]:
> https://github.com/mangopi-sbc/tina-linux-5.4/blob/main/drivers/soc/sunxi/g
> pu_domain.c [1]:
> https://github.com/mangopi-sbc/tina-linux-5.4/blob/main/drivers/soc/sunxi/p
> m_domains.c
> 
> 
> Samuel Holland (2):
>   dt-bindings: power: Add Allwinner D1 PPU
>   soc: sunxi: Add Allwinner D1 PPU driver
> 
>  .../power/allwinner,sun20i-d1-ppu.yaml        |  54 +++++
>  drivers/soc/sunxi/Kconfig                     |   9 +
>  drivers/soc/sunxi/Makefile                    |   1 +
>  drivers/soc/sunxi/sun20i-ppu.c                | 207 ++++++++++++++++++
>  .../power/allwinner,sun20i-d1-ppu.h           |  10 +
>  5 files changed, 281 insertions(+)
>  create mode 100644
> Documentation/devicetree/bindings/power/allwinner,sun20i-d1-ppu.yaml create
> mode 100644 drivers/soc/sunxi/sun20i-ppu.c
>  create mode 100644 include/dt-bindings/power/allwinner,sun20i-d1-ppu.h
Samuel Holland Jan. 26, 2023, 6:23 a.m. UTC | #2 
Hi Jernej,

On 1/5/23 10:34, Jernej Škrabec wrote:
> Dne sobota, 31. december 2022 ob 17:04:00 CET je Samuel Holland napisal(a):
>> This series adds support for the power controller found in D1 and other
>> recent Allwinner SoCs. There is no first-party documentation, but there
>> are a couple of vendor drivers for different hardware revisions[1][2],
>> and the register definitions were easy to verify empirically.
>>
>> I have tested this driver on D1 with the video engine. There is no DT
>> update patch here to avoid dependencies between series. The example in
>> the binding is what will go in the D1 DT.
> 
> So such driver is needed for H616 for GPU? Or is power domain handling 
> different there?

H616 does not appear to have a PPU. The PRCM gates otherwise match A100,
but there are no settable gate/reset bits at 0x17c, and the registers at
0x7001000 read as zero, even after being written. I believe H616 uses
only GPU_PWROFF_GATING_REG in the PRCM.

Regards,
Samuel