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[86.15.83.122]) by smtp.gmail.com with ESMTPSA id m5-20020adfc585000000b00236488f62d6sm3491610wrg.79.2022.12.23.07.38.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Dec 2022 07:38:23 -0800 (PST) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha , Ben Dooks Subject: [PATCH v7 00/10] Designware PWM driver updates for OF Date: Fri, 23 Dec 2022 15:38:10 +0000 Message-Id: <20221223153820.404565-1-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1753019786148323008?= X-GMAIL-MSGID: =?utf-8?q?1753019786148323008?= An updated set of patches for the Designware PWM driver split into PCI and OF versions. I think I got all the review issues in this set. Sorry for the delay in getting this out, between conferences and other absences there has been little time to deal with this set. I will be now out of office until 3rd Jan 2023. v7: - fixup kconfig from previous pcie changes - re-order kconfig to make dwc core be selected by PCI driver - move clk variable to patch it is used in v6: - fix removal ordering of DWC_PERIOD_NS v5: - fixed kconfig string error - merged pwm-nr into main of code - split of code from pci code - updated pwm-nr capping - fix duplicate error reporting in of-code - fix return in of-probe - remove unecessary remove function as devm_ functions sort this - fixed ordering of properties - added missing reg item - fixed missing split of the two clock sources. - get bus clock in of code v4: - split pci and of into new modules - fixup review comments - fix typos in dt-bindings v3: - change the compatible name - squash down pwm count patch - fixup patch naming v2: - fix #pwm-cells count to be 3 - fix indetation - merge the two clock patches - add HAS_IOMEM as a config dependency Ben Dooks (10): dt-bindings: pwm: Document Synopsys DesignWare snps,pwm-dw-apb-timers-pwm2 pwm: dwc: allow driver to be built with COMPILE_TEST pwm: dwc: change &pci->dev to dev in probe pwm: dwc: move memory alloc to own function pwm: dwc: use devm_pwmchip_add pwm: dwc: split pci out of core driver pwm: dwc: make timer clock configurable pwm: dwc: add of/platform support pwm: dwc: add PWM bit unset in get_state call pwm: dwc: use clock rate in hz to avoid rounding issues .../bindings/pwm/snps,dw-apb-timers-pwm2.yaml | 68 ++++++ drivers/pwm/Kconfig | 26 ++- drivers/pwm/Makefile | 2 + drivers/pwm/pwm-dwc-of.c | 76 +++++++ drivers/pwm/pwm-dwc-pci.c | 134 +++++++++++ drivers/pwm/pwm-dwc.c | 210 ++++-------------- drivers/pwm/pwm-dwc.h | 59 +++++ 7 files changed, 404 insertions(+), 171 deletions(-) create mode 100644 Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml create mode 100644 drivers/pwm/pwm-dwc-of.c create mode 100644 drivers/pwm/pwm-dwc-pci.c create mode 100644 drivers/pwm/pwm-dwc.h