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[2620:137:e000::1:20]) by mx.google.com with ESMTP id d23-20020a17090ad99700b0020af2b9dd80si8818664pjv.69.2022.12.02.22.48.37; Fri, 02 Dec 2022 22:48:50 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=i4E4W6Ok; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231340AbiLCGqt (ORCPT + 99 others); Sat, 3 Dec 2022 01:46:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34488 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229557AbiLCGqp (ORCPT ); Sat, 3 Dec 2022 01:46:45 -0500 Received: from mail-pf1-x435.google.com (mail-pf1-x435.google.com [IPv6:2607:f8b0:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6E30AB0A14 for ; Fri, 2 Dec 2022 22:46:44 -0800 (PST) Received: by mail-pf1-x435.google.com with SMTP id x66so6857358pfx.3 for ; Fri, 02 Dec 2022 22:46:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=QkYe9s/viJdr1lNCrRO9EfBEjk3e9FxStn28oqP+eFw=; b=i4E4W6OkgcQyekvb+8G0P20J9PGIXxHqnxwmj2dcOt0AzuWNVDhaGNgaSXvo9MQ0fa JnEm4fw/5GXKXecTSGYm5RO9TwIH1oKxEhitIM18xa4DEleoXs6BQ0b792bp/yNeZt1B uKgWQKHdIa76SWmqMxU2x5wo+mwcPM+EMHtR7R+ikJPCpCgkLxW1voki4ZLyhlrwrvT9 gKYIBqiz3dU8NktFBF93xVikY9v4I0Mrc0+npj2Y5M8McVCEJEv352vwx7rJfKXSJtGH RxIAtUS9xZH6KHuw7LMPDDa0bUpRGud86fXnUeURnVqcNge/AONMiDy3vTjLT9H5I3d9 V0Kw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=QkYe9s/viJdr1lNCrRO9EfBEjk3e9FxStn28oqP+eFw=; b=cbKrcEWmzZdYYMM2y73gq1mAor2sV61yTrP0zetMD2pH5CaQ7EbMSqfB/H3pibTRa9 91XHRzs7/PYV6Sje3VeIu2/blvrxJHBMvzspMp8pUnxTmuvOixMTEeJcFOvuwHA5KUjg aBs6CaXZANxfGt3+NMQu0T2Kijj39cCeJgkTijE974i5ItqxBjLMlicD4aEJ1nx5aBH0 mNFSqt4atKrrLpQdweGvdl1Im65+UWB8aRRDj2+raFJaZacVq4pWhYiHXPWmF3JHYcsl +tGJ5es1dn20HaN1PVMvUWz4L+Z9VuO5qX12eONA2gqp9fgU9Fu7ZbCnBHvhqw9W2qSR F2mA== X-Gm-Message-State: ANoB5pnwMpTZskqMwymjZLE3kEqRl9PoJFxIZnFKlrIAUunc9yuA86B8 NCRTuSAAodlHqvlonUM0OitjYA== X-Received: by 2002:a63:eb4b:0:b0:477:a350:2172 with SMTP id b11-20020a63eb4b000000b00477a3502172mr46294739pgk.167.1670050003749; Fri, 02 Dec 2022 22:46:43 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id t17-20020aa79471000000b00575c8242849sm6102091pfq.69.2022.12.02.22.46.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Dec 2022 22:46:43 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano Cc: Hector Martin , Sven Peter , Alyssa Rosenzweig , Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev, Anup Patel Subject: [PATCH v15 0/9] RISC-V IPI Improvements Date: Sat, 3 Dec 2022 12:16:20 +0530 Message-Id: <20221203064629.1601299-1-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751174485037369448?= X-GMAIL-MSGID: =?utf-8?q?1751174485037369448?= This series aims to improve IPI support in Linux RISC-V in following ways: 1) Treat IPIs as normal per-CPU interrupts instead of having custom RISC-V specific hooks. This also makes Linux RISC-V IPI support aligned with other architectures. 2) Remote TLB flushes and icache flushes should prefer local IPIs instead of SBI calls whenever we have specialized hardware (such as RISC-V AIA IMSIC and RISC-V SWI) which allows S-mode software to directly inject IPIs without any assistance from M-mode runtime firmware. These patches were originally part of the "Linux RISC-V ACLINT Support" series but this now a separate series so that it can be merged independently of the "Linux RISC-V ACLINT Support" series. (Refer, https://lore.kernel.org/lkml/20211007123632.697666-1-anup.patel@wdc.com/) These patches are also a preparatory patches for the up-coming: 1) Linux RISC-V AIA support 2) Linux RISC-V SWI support These patches can also be found in riscv_ipi_imp_v15 branch at: https://github.com/avpatel/linux.git Changes since v14: - Minor fixes in commit description of PATCH3 (as suggested by tglx) - Don't disable parent IPI when CPU goes offline for SBI IPI driver and CLINT driver in PATCH4. - Include Apple AIC driver changes from Marc Z as PATCH9 Changes since v13: - Included changes suggested by Marc Z in PATCH3 - Use chained handlers in PATCH4 - Added new PATCH8 to have empty irq_eoi() in RISC-V INTC driver. This avoids the unnecessary mask/unmask dance at time of handling interrupts. Changes since v12: - Rebased on Linux-6.1-rc7 - Bring-back the IPI optimization in ipi_mux_send_mask() for PATCH3 - Call ipi_mux_send() for one target CPU at a time in PATCH3 Changes since v11: - Removed ipi_mux_pre/post_handle() callbacks in PATCH3 - Removed sturct ipi_mux_ops in PATCH3 - Removed parent_virq and data pointer from everywhere in PATCH3 - Removed struct ipi_mux_control in PATCH3 - Improved function signature of ipi_mux_send() callback in PATCH3 - Used unsigned type with atomic operation in PATCH3 Changes since v10: - Rebased on Linux-6.1-rc5 - Drop the "!(pending & ibit)" check in ipi_mux_send_mask() of PATCH3 - Disable local interrupts in ipi_mux_send_mask() of PATCH3 because we can be preempted while using a per-CPU temporary variable. Changes since v9: - Rebased on Linux-6.1-rc3 - Updated header comment block of ipi-mux.c in PATCH3 - Use a struct for global data of ipi-mux.c in PATCH3 - Add per-CPU temp cpumask for sending IPIs in PATCH3 - Drop the use of fwspec in PATCH3 - Use static key for ipi_mux_pre_handle() and ipi_mux_post_handle() in PATCH3 - Remove redundant pr_warn_ratelimited() called by ipi_mux_process() in PATCH3 - Remove CPUHP thingy from ipi_mux_create() in PATCH3 Changes since v8: - Rebased on Linux-6.0-rc3 - Use dummy percpu data as parameter for request_percpu_irq() in PATCH4. Changes since v7: - Rebased on Linux-6.0-rc1 - Use atomic operations to track per-CPU pending and enabled IPIs in PATCH3. (Note: this is inspired from IPI muxing implemented in drivers/irqchip/irq-apple-aic.c) - Made "struct ipi_mux_ops" (added by PATCH3) flexible so that drivers/irqchip/irq-apple-aic.c can adopt it in future. Changes since v6: - Rebased on Linux-5.19-rc7 - Added documentation for struct ipi_mux_ops in PATCH3 - Dropped dummy irq_mask()/unmask() in PATCH3 - Added const for "ipi_mux_chip" in PATCH3 - Removed "type" initialization from ipi_mux_domain_alloc() in PATCH3 - Dropped translate() from "ipi_mux_domain_ops" in PATCH3 - Improved barrier documentation in ipi_mux_process() of PATCH3 - Added percpu check in ipi_mux_create() for parent_virq of PATCH3 - Added nr_ipi parameter in ipi_mux_create() of PATCH3 Changes since v5: - Rebased on Linux-5.18-rc3 - Used kernel doc style in PATCH3 - Removed redundant loop in ipi_mux_process() of PATCH3 - Removed "RISC-V" prefix form ipi_mux_chip.name of PATCH3 - Removed use of "this patch" in PATCH3 commit description - Addressed few other nit comments in PATCH3 Changes since v4: - Rebased on Linux-5.17 - Includes new PATCH3 which adds mechanism to multiplex a single HW IPI Changes since v3: - Rebased on Linux-5.17-rc6 - Updated PATCH2 to not export riscv_set_intc_hwnode_fn() - Simplified riscv_intc_hwnode() in PATCH2 Changes since v2: - Rebased on Linux-5.17-rc4 - Updated PATCH2 to not create synthetic INTC fwnode and instead provide a function which allows drivers to directly discover INTC fwnode Changes since v1: - Use synthetic fwnode for INTC instead of irq_set_default_host() in PATCH2 Anup Patel (8): RISC-V: Clear SIP bit only when using SBI IPI operations irqchip/riscv-intc: Allow drivers to directly discover INTC hwnode genirq: Add mechanism to multiplex a single HW IPI RISC-V: Treat IPIs as normal Linux IRQs RISC-V: Allow marking IPIs as suitable for remote FENCEs RISC-V: Use IPIs for remote TLB flush when possible RISC-V: Use IPIs for remote icache flush when possible irqchip/riscv-intc: Add empty irq_eoi() for chained irq handlers Marc Zyngier (1): irqchip/apple-aic: Move over to core ipi-mux arch/riscv/Kconfig | 2 + arch/riscv/include/asm/irq.h | 4 + arch/riscv/include/asm/sbi.h | 10 +- arch/riscv/include/asm/smp.h | 49 +++++-- arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/cpu-hotplug.c | 3 +- arch/riscv/kernel/irq.c | 21 ++- arch/riscv/kernel/sbi-ipi.c | 77 +++++++++++ arch/riscv/kernel/sbi.c | 100 +++------------ arch/riscv/kernel/smp.c | 166 ++++++++++++------------ arch/riscv/kernel/smpboot.c | 5 +- arch/riscv/mm/cacheflush.c | 5 +- arch/riscv/mm/tlbflush.c | 93 +++++++++++--- drivers/clocksource/timer-clint.c | 65 +++++++--- drivers/irqchip/Kconfig | 2 + drivers/irqchip/irq-apple-aic.c | 161 ++--------------------- drivers/irqchip/irq-riscv-intc.c | 71 ++++++---- include/linux/irq.h | 3 + kernel/irq/Kconfig | 5 + kernel/irq/Makefile | 1 + kernel/irq/ipi-mux.c | 207 ++++++++++++++++++++++++++++++ 21 files changed, 654 insertions(+), 397 deletions(-) create mode 100644 arch/riscv/kernel/sbi-ipi.c create mode 100644 kernel/irq/ipi-mux.c