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[2620:137:e000::1:20]) by mx.google.com with ESMTP id fj27-20020a0564022b9b00b0046a7c877f58si8897331edb.335.2022.11.28.10.49.55; Mon, 28 Nov 2022 10:50:22 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@aurel32.net header.s=202004.hall header.b=Shn+niV8; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232602AbiK1SsH (ORCPT + 99 others); Mon, 28 Nov 2022 13:48:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52720 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232492AbiK1Srt (ORCPT ); Mon, 28 Nov 2022 13:47:49 -0500 Received: from hall.aurel32.net (hall.aurel32.net [IPv6:2001:bc8:30d7:100::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ED05E1403C; Mon, 28 Nov 2022 10:47:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=aurel32.net ; s=202004.hall; h=Content-Transfer-Encoding:MIME-Version:Message-Id:Date: Subject:Cc:To:From:Content-Type:From:Reply-To:Subject:Content-ID: Content-Description:In-Reply-To:References:X-Debbugs-Cc; bh=2nc6ETieocz1/MF7D4a379nzMdeyEycYLQGwrA8DsAQ=; b=Shn+niV8Dwihi1yTofxwyKMWTu +zIt+swVCw1jCd4qzUK8xUpPMOupBnWuWw1qppfhsrrKQQzf1PFqSJChwmqV9iaRWW6YkmTI8WDA7 YQbaZjjCmF0JXrlDBBHlSxQAiZTpGe4D/tL5gy+HfjaMpNECY/aEe9Vp1PyxN5LaDPRZe/Ddde5nP le25Zdm3BNTreQI1LPlbYYhfa8jsFxpYQT1EgdlSyO9ByAY+jy7L83PTHnBK+vvW3sYbLhlPxz2m+ sqbPonHFgOSi8/TGjgho9yei9aH22ewVBzFG+va+qSO6d1pMrGFPIEtLnJHfpmqh4+Nqobx/EU7eb xnnrevqw==; Received: from [2a01:e34:ec5d:a741:8a4c:7c4e:dc4c:1787] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1ozjA2-006BV6-Ih; Mon, 28 Nov 2022 19:47:22 +0100 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.96) (envelope-from ) id 1ozjA1-008Ell-1p; Mon, 28 Nov 2022 19:47:21 +0100 From: Aurelien Jarno To: Olivia Mackall , Herbert Xu , Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Philipp Zabel , Lin Jinhan Cc: linux-crypto@vger.kernel.org (open list:HARDWARE RANDOM NUMBER GENERATOR CORE), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC support), linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support), linux-kernel@vger.kernel.org (open list), Aurelien Jarno Subject: [PATCH v2 0/3] hwrng: add hwrng support for Rockchip RK3568 Date: Mon, 28 Nov 2022 19:47:15 +0100 Message-Id: <20221128184718.1963353-1-aurelien@aurel32.net> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_PASS, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750766895541015510?= X-GMAIL-MSGID: =?utf-8?q?1750766895541015510?= Rockchip SoCs used to have a random number generator as part of their crypto device, and support for it has to be added to the corresponding driver. However newer Rockchip SoCs like the RK3568 have an independent True Random Number Generator device. This patchset adds a driver for it and enable it in the device tree. v1 -> v2: * Patch 1: fix issues reported by Rob Herring and Krzysztof Kozlowski: - Rename rockchip-rng.yaml into rockchip,rk3568-rng.yaml - Fix binding title and description - Fix compatible property - Rename clocks and add the corresponding descriptions - Drop reset-names - Add a bus definition with #address-cells and #size-cells to the example. * Patch 2: fix issue reported by kernel test robot - Do not read the random registers as big endian, looking at the RK3568 TRM this is actually not needed. This fixes a sparse warning. * Patch 3: unchanged Aurelien Jarno (3): dt-bindings: RNG: Add Rockchip RNG bindings hwrng: add Rockchip SoC hwrng driver arm64: dts: rockchip: add DT entry for RNG to RK356x .../bindings/rng/rockchip,rk3568-rng.yaml | 60 +++++ arch/arm64/boot/dts/rockchip/rk356x.dtsi | 9 + drivers/char/hw_random/Kconfig | 14 + drivers/char/hw_random/Makefile | 1 + drivers/char/hw_random/rockchip-rng.c | 250 ++++++++++++++++++ 5 files changed, 334 insertions(+) create mode 100644 Documentation/devicetree/bindings/rng/rockchip,rk3568-rng.yaml create mode 100644 drivers/char/hw_random/rockchip-rng.c