From patchwork Mon Nov 28 16:40:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 2322 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5819859wrr; Mon, 28 Nov 2022 09:13:06 -0800 (PST) X-Google-Smtp-Source: AA0mqf4BM6TB35JDXzBFd9rMhAfzn1MmjOLt4LkUCwibTVTAJkWj8Zs3ov3yE7e3rzMxnInUKF4i X-Received: by 2002:adf:db81:0:b0:236:5144:f8ce with SMTP id u1-20020adfdb81000000b002365144f8cemr25898859wri.657.1669655585680; Mon, 28 Nov 2022 09:13:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669655585; cv=none; d=google.com; s=arc-20160816; b=sB3R3Dq/X73pe/w9LglOZTqqbMBcAWCvaPp1D5L0DKFZjelrZY4eecfVGI5qvqPhOU K8oMbz8a2Ffdjx6cDSUIEGZfOqLqM3wyLJEa4aGHsaGq5ZEqJBhWa/VWehhieF9nyK1S CET27MySLqukrPyARdYoCuohn3OaRHYlvO7xCiSPVuoUVyf+EoUpHYGkmZLXzgoazfaj hNiQzaIWfFsBfd6sb8f1gp/bGUfqLIPhRk0FBU9qZKAkYGZ0fgqk+Fy0Y3jSntORXD4e UnpAUpTCh1NrGKtK3Fl40Vut5epb//Dn6X5xApSMh/gTydCWbzuEJVfJHz/VjbgMCBJ5 GU+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=I56ShMKxEBJo/6QU/baCmZqT6atQxlQpL9tjlX81W54=; b=qXXGQV46NXFCxGgA8mdm3hfsU9OfLExIcB7vGjPQ0o+MQ44JzHKFDes2yBXILKW20v HgW1hQZqa3RCmTCRHKFzUPUZPutOwQQlWYyqB4AdKI5JBrvuuNiEDsTAIFXWyFXj15Gu YC6/KVd+0F3lB6HugIp09pWdz/nMmJGLWXfUhTVEYszPTEBizA5nnwMIhY8Zxe0dsbYc eTqzmf1ZCtVayIairTOL9REgK9bc3pH898R8Ld9HIEbBoGAP1j72gFAbqKcPN4j7odB/ WFIFHhS3hID8jYm70E2iy9aTgm2PoUqHkbl/0ZZmOarOT4Ly3sVPWODaXM8Wt4K5ixF7 l/Yw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=dkDtTeYa; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id r18-20020a05640251d200b0046aaeca7d05si10109306edd.399.2022.11.28.09.12.41; Mon, 28 Nov 2022 09:13:05 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=dkDtTeYa; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231609AbiK1RFH (ORCPT + 99 others); Mon, 28 Nov 2022 12:05:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49606 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232225AbiK1REa (ORCPT ); Mon, 28 Nov 2022 12:04:30 -0500 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A4F2E644E for ; Mon, 28 Nov 2022 09:04:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1669655060; x=1701191060; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=+YkMR1rZQaFpNvTpwd9EMap2roQ2lgOxzhGZkaSG75Q=; b=dkDtTeYaWjDeE0S+ktMxo59GgGT+L+OjOdOqxbrn2bmzYL3bJhl5X0rX 7Hg4jXBrsnZpemsSlwPhblJuyu2FLpu+wvrFUuKvlGv01Mz8x65s/D+1K IPYUNsSqdm8eSf/4BmAYJPlvVqxuEvYkLKmZMSW0RffVxyuTuywvbtFpB dpg3MAn3W+w339cvM3+P9QbxCU2q05Du5U1zvxPcHEwYKYVhrhrG2uqjn uw1KjIY1QFBXJScjsDO5PSM3R0BNv0cHx7M04yR+2fgJ62g/Q63yfBoMT qxN1GjyGsJp31XWijQckLhl7AZfHWNaLIHnGs63H+yJzIk/IPr2S0nw17 g==; X-IronPort-AV: E=McAfee;i="6500,9779,10545"; a="313591609" X-IronPort-AV: E=Sophos;i="5.96,200,1665471600"; d="scan'208";a="313591609" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Nov 2022 09:04:20 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10545"; a="706864616" X-IronPort-AV: E=Sophos;i="5.96,200,1665471600"; d="scan'208";a="706864616" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga008.fm.intel.com with ESMTP; 28 Nov 2022 09:04:19 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, brgerst@gmail.com, chang.seok.bae@intel.com, jgross@suse.com Subject: [PATCH v5 0/5] x86: Enable LKGS instruction Date: Mon, 28 Nov 2022 08:40:23 -0800 Message-Id: <20221128164028.4570-1-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750760775200841393?= X-GMAIL-MSGID: =?utf-8?q?1750760775200841393?= LKGS instruction is introduced with Intel FRED (flexible return and event delivery) specification https://cdrdv2.intel.com/v1/dl/getContent/678938. LKGS is independent of FRED, so we enable it as a standalone CPU feature. LKGS behaves like the MOV to GS instruction except that it loads the base address into the IA32_KERNEL_GS_BASE MSR instead of the GS segment’s descriptor cache, which is exactly what Linux kernel does to load user level GS base. Thus, with LKGS, there is no need to SWAPGS away from the kernel GS base. Changes since v4: * Clear the LKGS feature from Xen PV guests (Juergen Gross). Changes since v3: * We want less ASM not more, thus keep local_irq_save/restore() inside native_load_gs_index() (Thomas Gleixner). * For paravirt enabled kernels, initialize pv_ops.cpu.load_gs_index to native_lkgs (Thomas Gleixner). Changes since V2: * Add "" not to show "lkgs" in /proc/cpuinfo (Chang S. Bae). * Mark DI as input and output (+D) as in V1, since the exception handler modifies it (Brian Gerst). Changes since V1: * Use EX_TYPE_ZERO_REG instead of fixup code in the obsolete .fixup code section (Peter Zijlstra). * Add a comment that states the LKGS_DI macro will be repalced with "lkgs %di" once the binutils support the LKGS instruction (Peter Zijlstra). H. Peter Anvin (Intel) (5): x86/cpufeature: add the cpu feature bit for LKGS x86/opcode: add the LKGS instruction to x86-opcode-map x86/gsseg: make asm_load_gs_index() take an u16 x86/gsseg: move load_gs_index() to its own new header file x86/gsseg: use the LKGS instruction if available for load_gs_index() arch/x86/entry/entry_64.S | 2 +- arch/x86/ia32/ia32_signal.c | 1 + arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/gsseg.h | 66 ++++++++++++++++++++++++ arch/x86/include/asm/mmu_context.h | 1 + arch/x86/include/asm/special_insns.h | 21 -------- arch/x86/kernel/cpu/common.c | 1 + arch/x86/kernel/paravirt.c | 1 + arch/x86/kernel/tls.c | 1 + arch/x86/lib/x86-opcode-map.txt | 1 + arch/x86/xen/enlighten_pv.c | 1 + tools/arch/x86/include/asm/cpufeatures.h | 1 + tools/arch/x86/lib/x86-opcode-map.txt | 1 + 13 files changed, 77 insertions(+), 22 deletions(-) create mode 100644 arch/x86/include/asm/gsseg.h