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Miller" <davem@davemloft.net>, Eric Dumazet <edumazet@google.com>, Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Jan Petrous <jan.petrous@nxp.com>, Ondrej Spacek <ondrej.spacek@nxp.com>, Ghennadi Procopciuc <Ghennadi.Procopciuc@nxp.com>, Andrew Lunn <andrew@lunn.ch> Cc: Chester Lin <clin@suse.com>, netdev@vger.kernel.org, s32@nxp.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Andreas_F=C3=A4rber?= <afaerber@suse.de>, Matthias Brugger <mbrugger@suse.com> Subject: [PATCH v2 0/5] Add GMAC support for S32 SoC family Date: Mon, 28 Nov 2022 13:49:15 +0800 Message-Id: <20221128054920.2113-1-clin@suse.com> X-Mailer: git-send-email 2.37.3 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: TYCP286CA0137.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:31b::15) To VI1PR0402MB3439.eurprd04.prod.outlook.com (2603:10a6:803:4::13) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: VI1PR0402MB3439:EE_|AS8PR04MB7655:EE_ X-MS-Office365-Filtering-Correlation-Id: fb54f2ea-b861-4aee-d3ed-08dad1045020 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Add GMAC support for S32 SoC family
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Message
Chester Lin
Nov. 28, 2022, 5:49 a.m. UTC
Hello, Here I want to introduce a new patch series, which aims to support GMAC functions on S32 SoCs, such as S32G2. This series is originally from NXP's implementation on CodeAurora[1] and it will be required by upstream kernel to configure platform settings at the DWMAC glue layer before activating the DWMAC core on different S32G boards. In this patchset I also introduce more register fields needed by S32 SoCs, such as higher CSR clock ranges and cache coherency settings. For more information please see NXP's GMACSUBSYS Reference Manual[2]. Currently, the whole architecture relies on FDTs offered by ATF[3] on CodeAurora to keep the flexibility of handling multiple S32 platforms since now S32 clks can be triggered via the ARM SCMI clock protocol and clk IDs/ settings can vary according to different board designs. To ensure that the driver can work properly, the dt-binding schemas in this patchset is still required as a reference. Thanks, Chester Changes in v2: - Fix schema issues. - Add minItems to clocks & clock-names. - Replace all sgmii/SGMII terms with pcs/PCS. - clock-names: tx_sgmii -> tx_pcs, rx_sgmii -> rx_pcs - Adjust error handlings while calling devm_clk_get(). - Remove redundant dev_info messages. - Remove unnecessary if conditions. - Fix the copyright format suggested by NXP. [1] https://source.codeaurora.org/external/autobsps32/linux/tree/drivers/net/ethernet/stmicro/stmmac?h=bsp34.0-5.10.120-rt [2] https://www.nxp.com/webapp/Download?colCode=GMACSUBSYSRM [3] https://source.codeaurora.org/external/autobsps32/arm-trusted-firmware/tag/?h=bsp34.0-2.5 Chester Lin (5): dt-bindings: net: snps, dwmac: add NXP S32CC support dt-bindings: net: add schema for NXP S32CC dwmac glue driver net: stmmac: Add CSR clock 500Mhz/800Mhz support net: stmmac: Add AXI4 ACE control support net: stmmac: Add NXP S32 SoC family support .../bindings/net/nxp,s32cc-dwmac.yaml | 135 ++++++++ .../devicetree/bindings/net/snps,dwmac.yaml | 5 +- drivers/net/ethernet/stmicro/stmmac/Kconfig | 13 + drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + drivers/net/ethernet/stmicro/stmmac/common.h | 2 + .../net/ethernet/stmicro/stmmac/dwmac-s32cc.c | 304 ++++++++++++++++++ .../net/ethernet/stmicro/stmmac/dwmac4_dma.c | 10 + .../net/ethernet/stmicro/stmmac/dwmac4_dma.h | 4 +- drivers/net/ethernet/stmicro/stmmac/hwif.h | 5 + .../net/ethernet/stmicro/stmmac/stmmac_main.c | 7 + include/linux/stmmac.h | 9 + 11 files changed, 492 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/net/nxp,s32cc-dwmac.yaml create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-s32cc.c