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Received: from VI1PR0402MB3439.eurprd04.prod.outlook.com (2603:10a6:803:4::13) by AS8PR04MB7829.eurprd04.prod.outlook.com (2603:10a6:20b:2a7::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5857.21; Mon, 28 Nov 2022 05:48:42 +0000 Received: from VI1PR0402MB3439.eurprd04.prod.outlook.com ([fe80::28d6:1b8:94d9:89f5]) by VI1PR0402MB3439.eurprd04.prod.outlook.com ([fe80::28d6:1b8:94d9:89f5%7]) with mapi id 15.20.5857.023; Mon, 28 Nov 2022 05:48:42 +0000 From: Chester Lin To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Dong Aisheng , Fabio Estevam , Shawn Guo , Jacky Bai Cc: Chester Lin , s32@nxp.com, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Pengutronix Kernel Team , Larisa Grigore , Ghennadi Procopciuc , Andrei Stefanescu , Radu Pirea , =?utf-8?q?Andreas_F=C3=A4rber?= , Matthias Brugger Subject: [PATCH v2 0/2] Add pinctrl support for S32 SoC family Date: Mon, 28 Nov 2022 13:48:18 +0800 Message-Id: <20221128054820.1771-1-clin@suse.com> X-Mailer: git-send-email 2.37.3 X-ClientProxiedBy: TYCP286CA0137.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:31b::15) To VI1PR0402MB3439.eurprd04.prod.outlook.com (2603:10a6:803:4::13) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: VI1PR0402MB3439:EE_|AS8PR04MB7829:EE_ X-MS-Office365-Filtering-Correlation-Id: 747d59b6-0280-4bc6-5809-08dad1043478 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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This series is originally from NXP's implementation on CodeAurora[1] and it will be required by upstream kernel for supporting a variety of devices on S32 SoCs which need to config PINMUXs, such as PHYs and MAC controllers. Currently, the whole architecture relies on FDTs offered by ATF[3] on CodeAurora to keep the flexibility of handling multiple S32 platforms since now S32 clks can be triggered via the ARM SCMI clock protocol and clk IDs/ settings can vary according to different board designs. To ensure that the driver can work properly, the dt-binding schemas in this patchset are still required as references. Thanks, Chester Changes in v2: - Move the "nxp,pins" ID range information from DT to the driver. - dt-bindings: - Fix schema issues. - Add descriptions for reg entries. - Revise the example. - Refine the compatible name from "nxp,s32g-..." to "nxp,s32g2-...". - Fix the copyright format suggested by NXP. [1] https://source.codeaurora.org/external/autobsps32/linux/tree/drivers/pinctrl/freescale?h=bsp34.0-5.10.120-rt [2] https://source.codeaurora.org/external/autobsps32/arm-trusted-firmware/tag/?h=bsp34.0-2.5 Chester Lin (2): dt-bindings: pinctrl: add schema for NXP S32 SoCs pinctrl: add NXP S32 SoC family support .../pinctrl/nxp,s32cc-siul2-pinctrl.yaml | 125 ++ drivers/pinctrl/freescale/Kconfig | 16 + drivers/pinctrl/freescale/Makefile | 2 + drivers/pinctrl/freescale/pinctrl-s32.h | 77 ++ drivers/pinctrl/freescale/pinctrl-s32cc.c | 1003 +++++++++++++++++ drivers/pinctrl/freescale/pinctrl-s32g.c | 773 +++++++++++++ 6 files changed, 1996 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/nxp,s32cc-siul2-pinctrl.yaml create mode 100644 drivers/pinctrl/freescale/pinctrl-s32.h create mode 100644 drivers/pinctrl/freescale/pinctrl-s32cc.c create mode 100644 drivers/pinctrl/freescale/pinctrl-s32g.c