Message ID | 20221124125225.24538-1-moudy.ho@mediatek.com |
---|---|
Headers |
Return-Path: <linux-kernel-owner@vger.kernel.org> Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp3378441wrr; Thu, 24 Nov 2022 04:56:18 -0800 (PST) X-Google-Smtp-Source: AA0mqf4RQqVKNslUZ4HqZX0Gog6xmhWa40DcyybpU0/Zw9vCz9LgejSx1+5F0oKQVDd7UyesoccF X-Received: by 2002:a05:6402:4147:b0:461:b2b1:9702 with SMTP id x7-20020a056402414700b00461b2b19702mr14222935eda.274.1669294578298; Thu, 24 Nov 2022 04:56:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669294578; cv=none; d=google.com; s=arc-20160816; b=WOq9Q2SF6mfxfIIOwySbEG6X1vjP2RvNBzKaLdqxdvOwGx+HYG5SGpwTm86X95qOB/ /5BcfftwUXWLEIM7Ip0BrlNuvaReByzOPLWpE58z6P//Aa/P0j/hy6E5A/uc28vOF+rh tdXIoqG/QorypgRTchUcUQoYXNDVuT651czmFj8nH8Xa1y6AD01d1U2TKUu2rNDBJVlu TP2JMLIlhBx8Zez+hHCvZewbCoCY5PVyc2t7tml2g8Bi/kBzEOPX1EZCnDhBAiabRO2K CXo/iLNZDOfyjttgX6eflX8gt4NYC9QGYyn98NBwbGA0eyP8+SoYLTD50oUdo9aoV85a nyzg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:message-id:date:subject:cc:to:from :dkim-signature; bh=dIlDFzZFBnSE9uDVKb1CWs4x9E8Ao4H4ickzs3UqjcM=; b=TNh2sSNOs+liyrmnEK+xq/uFXUodzfMiWiNDvkOnaIce4N8BcL+eCazVBkzbrKSZ/m GdQU/YGuf9DoRqZrBktxf/27kQCXZu99ehI+HafMf68dXPKCBrwiYy+y7zUTfYcya1X9 wqqPXS+3UXEEqq6jjMBHvGEF/9NfNtW/a2PKVDkgJgAbA5ztI/tYPd+ApFMissqzYyts sbAnMQl9aRPFXwwcuSu7Wd81s10TaTURo6OjgZovsK/Ab7v7diJ7Ox0wIxYlm+alFw5G 6c2s3z/r9odQ4anJFXCYifTZuZF7ge4BEZW0NbDHcE3k0z75twX/fiUrzexMpP4v5XH9 Umdw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=m14zb5hL; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id eg48-20020a05640228b000b0046a353c3b73si867416edb.280.2022.11.24.04.55.55; Thu, 24 Nov 2022 04:56:18 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=m14zb5hL; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229842AbiKXMwi (ORCPT <rfc822;fengqi706@gmail.com> + 99 others); Thu, 24 Nov 2022 07:52:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36666 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229813AbiKXMwd (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Thu, 24 Nov 2022 07:52:33 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6A90B6570; Thu, 24 Nov 2022 04:52:32 -0800 (PST) X-UUID: 59c180c8c7fa47e1971d7b43d8235852-20221124 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=dIlDFzZFBnSE9uDVKb1CWs4x9E8Ao4H4ickzs3UqjcM=; b=m14zb5hLXLiMFkCdhM5XwbF2b40SJgGUf+IavoI1oOzVyFAV8dwa96ELmq+2dnekqhwowkkS75TrdqmLpMAhRJbEloIJDveNYRBY4mBLMBWhWk6qy0yIuVRnplF9PobnBqwXVRPJ+MAM+0dLtJgV16wAsPdACXuI4Gt+labzyY8=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.14,REQID:68b9f097-3ac0-49f7-b7ff-e38f9d92048e,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:dcaaed0,CLOUDID:2b17bb2f-2938-482e-aafd-98d66723b8a9,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 59c180c8c7fa47e1971d7b43d8235852-20221124 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw01.mediatek.com (envelope-from <moudy.ho@mediatek.com>) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 2094642625; Thu, 24 Nov 2022 20:52:28 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Thu, 24 Nov 2022 20:52:26 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Thu, 24 Nov 2022 20:52:27 +0800 From: Moudy Ho <moudy.ho@mediatek.com> To: Mauro Carvalho Chehab <mchehab@kernel.org>, Matthias Brugger <matthias.bgg@gmail.com>, Hans Verkuil <hverkuil-cisco@xs4all.nl> CC: Chun-Kuang Hu <chunkuang.hu@kernel.org>, <linux-media@vger.kernel.org>, <linux-mediatek@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <Project_Global_Chrome_Upstream_Group@mediatek.com>, Moudy Ho <moudy.ho@mediatek.com> Subject: [PATCH v1 00/12] add support MDP3 on MT8195 platform Date: Thu, 24 Nov 2022 20:52:13 +0800 Message-ID: <20221124125225.24538-1-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 Content-Type: text/plain X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, SPF_PASS,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750382231907246865?= X-GMAIL-MSGID: =?utf-8?q?1750382231907246865?= |
Series |
add support MDP3 on MT8195 platform
|
|
Message
Moudy Ho (何宗原)
Nov. 24, 2022, 12:52 p.m. UTC
Hello, This patch is used to add support for MDP3 on the MT8195 platform that contains more picture quality components, and can arrange more pipelines through two sets of MMSYS and MUTEX respectively. This series are based on following series: [1] MDP3 : https://patchwork.kernel.org/project/linux-mediatek/list/?series=698872 [2] MMSYS/MUTEX: https://patchwork.kernel.org/project/linux-mediatek/list/?series=684959 Moudy Ho (12): dt-binding: mediatek: add bindings for MediaTek 8195 MDP3 components arm64: dts: mediatek: mt8195: add MDP3 nodes media: platform: mtk-mdp3: add support second sets of MMSYS media: platform: mtk-mdp3: add support second sets of MUTEX media: platform: mtk-mdp3: introduce more pipelines from 8195 media: platform: mtk-mdp3: introduce more MDP3 components media: platform: mtk-mdp3: add checks for dummy components media: platform: mtk-mdp3: avoid multiple driver registrations media: platform: mtk-mdp3: extend GCE event waiting in RDMA and WROT media: platform: mtk-mdp3: add 8195 platform configuration media: platform: mtk-mdp3: add 8195 shared memory configurations media: platform: mtk-mdp3: add 8195 component settings .../bindings/media/mediatek,mdp3-aal.yaml | 64 ++ .../bindings/media/mediatek,mdp3-color.yaml | 64 ++ .../bindings/media/mediatek,mdp3-fg.yaml | 64 ++ .../bindings/media/mediatek,mdp3-hdr.yaml | 63 ++ .../bindings/media/mediatek,mdp3-merge.yaml | 64 ++ .../bindings/media/mediatek,mdp3-ovl.yaml | 64 ++ .../bindings/media/mediatek,mdp3-pad.yaml | 64 ++ .../bindings/media/mediatek,mdp3-rdma.yaml | 5 +- .../bindings/media/mediatek,mdp3-split.yaml | 76 ++ .../bindings/media/mediatek,mdp3-stitch.yaml | 64 ++ .../bindings/media/mediatek,mdp3-tcc.yaml | 63 ++ .../bindings/media/mediatek,mdp3-tdshp.yaml | 64 ++ arch/arm64/boot/dts/mediatek/mt8195.dtsi | 398 +++++++++ .../platform/mediatek/mdp3/mdp_reg_aal.h | 25 + .../platform/mediatek/mdp3/mdp_reg_color.h | 31 + .../media/platform/mediatek/mdp3/mdp_reg_fg.h | 23 + .../platform/mediatek/mdp3/mdp_reg_hdr.h | 31 + .../platform/mediatek/mdp3/mdp_reg_merge.h | 25 + .../platform/mediatek/mdp3/mdp_reg_ovl.h | 25 + .../platform/mediatek/mdp3/mdp_reg_pad.h | 21 + .../platform/mediatek/mdp3/mdp_reg_rdma.h | 24 + .../platform/mediatek/mdp3/mdp_reg_rsz.h | 2 + .../platform/mediatek/mdp3/mdp_reg_tdshp.h | 34 + .../platform/mediatek/mdp3/mdp_reg_wrot.h | 8 + .../mediatek/mdp3/mt8183/mdp3-plat-mt8183.h | 46 +- .../mediatek/mdp3/mt8195/mdp3-comp-mt8195.h | 283 ++++++ .../mediatek/mdp3/mt8195/mdp3-plat-mt8195.h | 652 ++++++++++++++ .../platform/mediatek/mdp3/mtk-img-ipi.h | 4 + .../platform/mediatek/mdp3/mtk-mdp3-cmdq.c | 257 +++++- .../platform/mediatek/mdp3/mtk-mdp3-comp.c | 834 +++++++++++++++++- .../platform/mediatek/mdp3/mtk-mdp3-comp.h | 86 +- .../platform/mediatek/mdp3/mtk-mdp3-core.c | 94 +- .../platform/mediatek/mdp3/mtk-mdp3-core.h | 21 + 33 files changed, 3529 insertions(+), 114 deletions(-) create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-aal.yaml create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-color.yaml create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-merge.yaml create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-ovl.yaml create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-pad.yaml create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-split.yaml create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_aal.h create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_color.h create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_fg.h create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_hdr.h create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_merge.h create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_ovl.h create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_pad.h create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_tdshp.h create mode 100644 drivers/media/platform/mediatek/mdp3/mt8195/mdp3-comp-mt8195.h create mode 100644 drivers/media/platform/mediatek/mdp3/mt8195/mdp3-plat-mt8195.h