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From: Manikanta Maddireddy <mmaddireddy@nvidia.com>
To: <vkoul@kernel.org>, <kishon@kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>, <thierry.reding@gmail.com>,
<jonathanh@nvidia.com>, <vidyas@nvidia.com>
CC: <linux-phy@lists.infradead.org>, <devicetree@vger.kernel.org>,
<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-pci@vger.kernel.org>, <bhelgaas@google.com>,
<lpieralisi@kernel.org>, <nkristam@nvidia.com>,
Manikanta Maddireddy <mmaddireddy@nvidia.com>
Subject: [IP REVIEW PATCH 0/3] Add support for Lane Margining at Receiver
Date: Thu, 24 Nov 2022 14:05:07 +0530
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| Series |
Add support for Lane Margining at Receiver
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Message
Manikanta Maddireddy
Nov. 24, 2022, 8:35 a.m. UTC
Tegra234 supports Lane Margining at Receiver feature. However, this requires programming of per lane PIPE2UPHY hardware instance to relay the lane margin control and margin status information between PCIe controller and UPHY modules. This series adds this support in PIPE2UPHY driver. Manikanta Maddireddy (3): phy: tegra: p2u: Add lane margin support dts: soc: t234: Add uphy lane number and intr in p2u nodes dt-bindings: PHY: P2U: Add PCIe lane margining support .../bindings/phy/phy-tegra194-p2u.yaml | 50 ++++ arch/arm64/boot/dts/nvidia/tegra234.dtsi | 120 ++++++++ drivers/phy/tegra/phy-tegra194-p2u.c | 274 ++++++++++++++++++ 3 files changed, 444 insertions(+)