mbox series

[0/2] These are the required patches I found while adding

Message ID 20221123211335.126417-1-nathan.morrison@timesys.com
Headers
Series These are the required patches I found while adding |

Message

Nathan Barrett-Morrison Nov. 23, 2022, 9:13 p.m. UTC 
  1) The core framework needs some additional logic for 8S-8S-8S to pass through
succesfully.

2) The IS25LX256 chip needs added to the SPI part table along with various fixups

Nathan Barrett-Morrison (2):
  mtd: spi-nore: core: Add in framework for 8S-8S-8S Octal STR mode
  mtd: spi-nor: issi: Add in support for IS25LX256 chip, operating in
    Octal STR mode

 drivers/mtd/spi-nor/core.c |  57 ++++++++++++++++++++-
 drivers/mtd/spi-nor/core.h |   5 +-
 drivers/mtd/spi-nor/issi.c | 101 +++++++++++++++++++++++++++++++++++++
 3 files changed, 160 insertions(+), 3 deletions(-)

Comments

Michael Walle Nov. 24, 2022, 8:07 a.m. UTC | #1 
Hi Nathan,

Am 2022-11-23 22:13, schrieb Nathan Barrett-Morrison:
> 1) The core framework needs some additional logic for 8S-8S-8S to pass 
> through
> succesfully.
> 
> 2) The IS25LX256 chip needs added to the SPI part table along with
> various fixups

Unfortunately, I can't make any sense of this series. First of all, the
IS25LX256 [1] doesn't support 8S-8S-8S, only 8D-8D-8D and 1S-8S-8S, see
ch. 4. Confused, I've looked at your octal str enable function and it 
writes
0xc7 to the volatile configuration register 0x00. According to the 
datasheet,
that is the enable for the octal DTR mode.

Please explain your problem and your motivation in the cover 
letter/commit
message and how you fix it.

[1] https://www.issi.com/WW/pdf/25LX-WX256-128.pdf

-michael
Nathan Barrett-Morrison Nov. 24, 2022, 11:47 a.m. UTC | #2 
Hi Michael,

Ah yes, I just realized we're effectively using the device in 1S-1S-8S extended SPI mode, so the 0xC7 setting is probably not required.  We were never able to get DTR mode working on the IS25LX256.  I can fix this patch up so it's more explicit about what's going on here.

The 8S-8S-8S support in core.c is still going to be used for another OSPI device I'm porting over from an older kernel.

Would you like me to separate these patches, fix up the ISSI once, and resubmit?

Sincerely,
Nathan
Michael Walle Nov. 24, 2022, 12:42 p.m. UTC | #3 
Hi,

Am 2022-11-24 12:47, schrieb Nathan Barrett-Morrison:
> Ah yes, I just realized we're effectively using the device in 1S-1S-8S
> extended SPI mode, so the 0xC7 setting is probably not required.  We
> were never able to get DTR mode working on the IS25LX256. I can fix
> this patch up so it's more explicit about what's going on here.
> 
> The 8S-8S-8S support in core.c is still going to be used for another
> OSPI device I'm porting over from an older kernel.

Can you link a datasheet? The problem with 8s8s8s is that it needs
mode switching which can be footgun. And IMHO it doesn't provide
significant performance improvements over 1s8s8s.

> Would you like me to separate these patches, fix up the ISSI once, and 
> resubmit?

Yes please. Also, I've seen that you use flags in the flash_info table.
Please have a look if that information can be deduced from the SFDP. 
E.g.
does a flash describe if it supports 1s1s8s.

-michael