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[2620:137:e000::1:20]) by mx.google.com with ESMTP id g130-20020a636b88000000b0045a2d89c9cfsi13633957pgc.348.2022.11.22.02.17.52; Tue, 22 Nov 2022 02:18:07 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=e5LZ9zz6; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232715AbiKVKQh (ORCPT + 99 others); Tue, 22 Nov 2022 05:16:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42922 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232695AbiKVKQc (ORCPT ); Tue, 22 Nov 2022 05:16:32 -0500 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 50AF23FBB6; Tue, 22 Nov 2022 02:16:31 -0800 (PST) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2AMAGL3s008091; Tue, 22 Nov 2022 04:16:21 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1669112181; bh=tYP7bqAx/cpfj7hfCOdeukndTpMlP7LdDZ9xIHmCnMU=; h=From:To:CC:Subject:Date; b=e5LZ9zz6NyRdyw8/xyTU4WYJo0JJCMkfyCeo2vsohsX5PuIFrVpYBN4l+OWAkZjpM xF3etaJVlHhE/JgIi1ZQkJkAAB+7hsojNPKp5RjkrzMHkfsAkuIib8oTosefDVmFjJ Z0QXZLfGOVjiu3tG+7AHOzFoH/Xv0WIFq3y9t0DA= Received: from DLEE106.ent.ti.com (dlee106.ent.ti.com [157.170.170.36]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2AMAGL0q079438 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 22 Nov 2022 04:16:21 -0600 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Tue, 22 Nov 2022 04:16:21 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Tue, 22 Nov 2022 04:16:21 -0600 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2AMAGING029863; Tue, 22 Nov 2022 04:16:19 -0600 From: Matt Ranostay To: , , , , , , , CC: , , Subject: [PATCH v7 0/8] arm64: j721s2: Add support for additional IPs Date: Tue, 22 Nov 2022 02:16:08 -0800 Message-ID: <20221122101616.770050-1-mranostay@ti.com> X-Mailer: git-send-email 2.38.GIT MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750191085296837841?= X-GMAIL-MSGID: =?utf-8?q?1750191085296837841?= The following series of patches add support for the following on J721S2 common processor board, - USB - SerDes - OSPI - PCIe Changes from v1: * Resolve issues with dt schema reporting * Minor changes related to consistency on node naming and value Changes from v2: * Added PCIe RC + EP enablement patchsets * Added device-id for j722s2 PCIe host in dt documentation * Reworked SERDES + WIZ enablement patchset to use properies for clocks defines versus entire devicetree nodes. Results in cleaner code that doesn't break dt-schema or the driver functionality. Changes from v3: * Rebased changes on top of '[PATCH 00/12] TI J7x Disable Incomplete DT Nodes' * Removed "dt-bindings: PCI: Add host mode device-id for j721s2 platform" patch and send it own series to avoid a dependency that would hold up other patches in this series Changes from v4: * Add my Signed-off-by lines to all patchsets Changes from v5: * Removed Cc from commit messages to reduce clutter * Squashed changes for device tree nodes that get modified latter in the patchset series Changes from v6: * Changes to ti,j721s2-wiz-10g compatible string from ti,am64-wiz-10g but requires this series to be merged first Ref: https://lore.kernel.org/linux-arm-kernel/20221122092203.762308-1-mranostay@ti.com/ * Removed unused pcie1_ep based on feedback * Switch from incorrect "ti,j721e-system-controller", "syscon", "simple-mfd" compatible for SPI node to "simple-bus" Aswath Govindraju (7): arm64: dts: ti: k3-j721s2-main: Add support for USB arm64: dts: ti: k3-j721s2-mcu-wakeup: Add support of OSPI arm64: dts: ti: k3-j721s2-common-proc-board: Enable SERDES0 arm64: dts: ti: k3-j721s2-common-proc-board: Add USB support arm64: dts: ti: k3-j721s2: Add support for OSPI Flashes arm64: dts: ti: k3-j721s2-main: Add PCIe device tree node arm64: dts: ti: k3-j721s2-common-proc-board: Enable PCIe Matt Ranostay (1): arm64: dts: ti: k3-j721s2-main: Add SERDES and WIZ device tree node .../dts/ti/k3-j721s2-common-proc-board.dts | 85 +++++++++++ arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 137 ++++++++++++++++++ .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 40 +++++ arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 42 ++++++ 4 files changed, 304 insertions(+)