mbox series

[v5,0/7] pinctrl: intel: Enable PWM optional feature

Message ID 20221117110806.65470-1-andriy.shevchenko@linux.intel.com
Headers
Series pinctrl: intel: Enable PWM optional feature |

Message

Andy Shevchenko Nov. 17, 2022, 11:07 a.m. UTC 
  This is a continuation of the previously applied PWM LPSS cleanup series.
Now, we would like to enable PWM optional feature that may be embedded
into Intel pin control IPs (starting from Sky Lake platforms).

I would like to route this via Intel pin control tree with issuing
an immutable branch for both PINCTRL and PWM subsystems, but I'm
open for other suggestions.

Hans, I dared to leave your Rb tags, however the patches are slightly
differ, because of the Uwe's suggestion on how to handle the missing
headers. I hope you are okay with that. If not, please comment what
must be amended then.

Uwe, the patches 3 and 6 still need your blessing.

Changelog v5:
- added more tags (Uwe)
- avoid moving struct pwm_lpss_chip in patch 3 (Uwe)
- simplified error checking in intel_pinctrl_probe_pwm() (Uwe)

Changelog v4:
- added patch "Rename pwm_lpss_probe() --> devm_pwm_lpss_probe()"

Changelog v3:
- added tags (Uwe, Linus, Thierry)
- fixed some spelling issues in the commit messages
- changed a paragraph in the commit message of the patch 3 (Uwe)
- replaced -ENODEV check with IS_REACHABLE() in the patch 6 (Uwe)

Changelog v2:
- added tag (Mika)
- added base-commit to the series, to make sure LKP can test it

Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Mika Westerberg <mika.westerberg@linux.intel.com>

Andy Shevchenko (7):
  pwm: Add a stub for devm_pwmchip_add()
  pwm: lpss: Rename MAX_PWMS --> LPSS_MAX_PWMS
  pwm: lpss: Include headers we are the direct user of
  pwm: lpss: Allow other drivers to enable PWM LPSS
  pwm: lpss: Rename pwm_lpss_probe() --> devm_pwm_lpss_probe()
  pwm: lpss: Add devm_pwm_lpss_probe() stub
  pinctrl: intel: Enumerate PWM device when community has a capability

 drivers/pinctrl/intel/pinctrl-intel.c      | 29 ++++++++++++++
 drivers/pwm/pwm-lpss-pci.c                 |  2 +-
 drivers/pwm/pwm-lpss-platform.c            |  2 +-
 drivers/pwm/pwm-lpss.c                     |  8 ++--
 drivers/pwm/pwm-lpss.h                     | 26 ++-----------
 include/linux/platform_data/x86/pwm-lpss.h | 44 ++++++++++++++++++++++
 include/linux/pwm.h                        |  5 +++
 7 files changed, 88 insertions(+), 28 deletions(-)
 create mode 100644 include/linux/platform_data/x86/pwm-lpss.h


base-commit: 9abf2313adc1ca1b6180c508c25f22f9395cc780

Comments

Andy Shevchenko Nov. 22, 2022, 1 p.m. UTC | #1 
On Thu, Nov 17, 2022 at 01:07:59PM +0200, Andy Shevchenko wrote:
> 
> This is a continuation of the previously applied PWM LPSS cleanup series.
> Now, we would like to enable PWM optional feature that may be embedded
> into Intel pin control IPs (starting from Sky Lake platforms).
> 
> I would like to route this via Intel pin control tree with issuing
> an immutable branch for both PINCTRL and PWM subsystems, but I'm
> open for other suggestions.
> 
> Hans, I dared to leave your Rb tags, however the patches are slightly
> differ, because of the Uwe's suggestion on how to handle the missing
> headers. I hope you are okay with that. If not, please comment what
> must be amended then.
> 
> Uwe, the patches 3 and 6 still need your blessing.

Uwe, do you think they are ready to go?