From patchwork Thu Nov 10 01:42:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1419 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp667639wru; Wed, 9 Nov 2022 17:46:30 -0800 (PST) X-Google-Smtp-Source: AMsMyM7P50fr6LnAfpxcjHr8jCx7us/8PSUJoyVygqTryvG3w8mjmC7GWa7vopKOeG39zIzv5ydd X-Received: by 2002:aa7:80d6:0:b0:53e:7332:709d with SMTP id a22-20020aa780d6000000b0053e7332709dmr1560670pfn.56.1668044790366; Wed, 09 Nov 2022 17:46:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668044790; cv=none; d=google.com; s=arc-20160816; b=Y4y/k72oU+kJ3MkZiurOS9T63Nw/UjodASoNy71gU7hcKPQFbvwL9X8+dGNLA2uS0Q khCdXn5v/xsMupfLSssZT1+YJwtm9AGREU4PZ3BMWX0OQ3Y5DETGEuprtf7cXeTY78Yo gMDEIOEw6n4zry6EXVmEASwpgcK9z3Cr6F5PV2rmeOlzsY4zJ73udcGV5VL/n5ua13og Kyew+/fD5KR2pCranvUUFdyf23v8I23LbGk7vaNRYPvnNxV6rqFPSNMqJQSBmsMi2wCs EGnDEM+IS82gUHGks1u3H5HM5LW7ZxkdRsk4HF1eiUs0TSy4xGhj5fuuyOPEIzh1sPAs XtsA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=K86r1wCoJyLnC5tX9TLKFyIQUcBXzk1URF/q8+n4zqs=; b=NzXHRywBCtiFwB5YThF0k9dkEppISS7rtS95NbOjluJ0Wc0tyoMAr3uOx9RrJf1dKM Yt+X71hwtKX6QehQtU//RY1RuIbCP+nDLQghr3cm/oouFW9xFFlDH5JuN85uktTxbIAZ SfuX6kkkp3for5DuMx/GaFlVGDTDBNckfm7eP3bnD4fzxustlzB4PLwKxbditB1182CJ zLg+nddN5vo6Z7QLXZ4qxblsNogs7zLKyK9jed3EpV4q0yXAqAi52vZTp7GmLq0Y5mMU IARanYtLXifYLsOVAXzfdAOWjjgx6DmVxgTn5xhNbIk9ZyWUI5srVTrb76M5xSx9tJyd /0Lg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id b11-20020a056a00114b00b0056c94208afcsi20884032pfm.6.2022.11.09.17.46.16; Wed, 09 Nov 2022 17:46:30 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231215AbiKJBoY (ORCPT + 99 others); Wed, 9 Nov 2022 20:44:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42740 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229784AbiKJBoX (ORCPT ); Wed, 9 Nov 2022 20:44:23 -0500 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 274BA275E2; Wed, 9 Nov 2022 17:44:22 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E8B671FB; Wed, 9 Nov 2022 17:44:27 -0800 (PST) Received: from slackpad.fritz.box (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3AF633F703; Wed, 9 Nov 2022 17:44:20 -0800 (PST) From: Andre Przywara To: Linus Walleij , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Icenowy Zheng , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev Subject: [RFC PATCH 0/2] pinctrl: sunxi: Introduce DT-based pinctrl builder Date: Thu, 10 Nov 2022 01:42:53 +0000 Message-Id: <20221110014255.20711-1-andre.przywara@arm.com> X-Mailer: git-send-email 2.35.5 MIME-Version: 1.0 X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749071734020422457?= X-GMAIL-MSGID: =?utf-8?q?1749071734020422457?= Hi, since the dawn of time every Allwinner SoC dumped a rather large table of data into the kernel, to describe the mapping between the pinctrl function name and its mux value, for each pin. This series introduces code that avoids that (for new SoCs), by instead reading that information directly from the devicetree. We have per-pin group nodes there anyway, and were just missing the mux value. Compared to my previous effort almost exactly five years ago [1], this new version drops the idea of describing the pinctrl data entirely in the DT, instead it still relies on driver provided information for that. That is more flexible, since it allows to introduce quirks and special handling more cleanly, at the cost of still requiring a separate driver file for each SoC. However this file is now very small, and can be easily written and reviewed. All that is needed is the number of pins per bank, plus information about each bank's IRQ capability. Patch 2/2 shows an example, for the yet unsupported Allwinner V5 SoC. On the DT side all that would be needed is *one* extra property per pin group to announce the mux value: uart0_pb_pins: uart0-pb-pins { pins = "PB9", "PB10"; function = "uart0"; pinmux = <2>; }; The new code works by providing a function that builds the former mapping table *at runtime*, by using both the driver provided information, plus traversing all children of the pinctrl DT node, to find all pin groups needed. This table looks the same as what we hardcoded so far, so can easily be digested by the existing sunxi pinctrl driver. Please have a look and tell me whether this new approach has a better future than my previous attempt. Cheers, Andre [1] https://patchwork.ozlabs.org/project/linux-gpio/cover/20171113012523.2328-1-andre.przywara@arm.com/ Andre Przywara (2): pinctrl: sunxi: allow reading mux values from DT pinctrl: sunxi: Add support for the Allwinner V5 pin controller drivers/pinctrl/sunxi/Kconfig | 5 + drivers/pinctrl/sunxi/Makefile | 2 + drivers/pinctrl/sunxi/pinctrl-sun8i-v5.c | 52 ++++ drivers/pinctrl/sunxi/pinctrl-sunxi-dt.c | 355 +++++++++++++++++++++++ drivers/pinctrl/sunxi/pinctrl-sunxi.h | 8 + 5 files changed, 422 insertions(+) create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-v5.c create mode 100644 drivers/pinctrl/sunxi/pinctrl-sunxi-dt.c