mbox series

[v2,0/6] pinctrl: intel: Enable PWM optional feature

Message ID 20221108142226.63161-1-andriy.shevchenko@linux.intel.com
Headers
Series pinctrl: intel: Enable PWM optional feature |

Message

Andy Shevchenko Nov. 8, 2022, 2:22 p.m. UTC 
  This is a continuation of the previously applied PWM LPSS cleanup series.
Now, we would like to enable PWM optional feature that may be embedded
into Intel pin control IPs (starting from Sky Lake platforms).

I would like to route this via Intel pin control tree with issuing
an immutable branch for both PINCTRL and PWM subsystems, but I'm
open for other suggestions.

Hans, I dared to leave your Rb tags, however the patches are slighly
differ, because of the Uwe's suggestion on how to handle the missing
headers. I hope you is okay with that. If not, please comment what
must be ammended then.

Changelog v2:
- added tag (Mika)
- added base-commit to the series, to make sure LKP can test it

Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Mika Westerberg <mika.westerberg@linux.intel.com>

Andy Shevchenko (6):
  pwm: Add a stub for devm_pwmchip_add()
  pwm: lpss: Rename MAX_PWMS --> LPSS_MAX_PWMS
  pwm: lpss: Include headers we are direct user of
  pwm: lpss: Allow other drivers to enable PWM LPSS
  pwm: lpss: Add pwm_lpss_probe() stub
  pinctrl: intel: Enumerate PWM device when community has a capabilitty

 drivers/pinctrl/intel/pinctrl-intel.c         | 29 +++++++++++++
 drivers/pwm/pwm-lpss.c                        |  2 +-
 drivers/pwm/pwm-lpss.h                        | 34 ++++-----------
 .../linux/platform_data/x86}/pwm-lpss.h       | 41 ++++++++-----------
 include/linux/pwm.h                           |  5 +++
 5 files changed, 61 insertions(+), 50 deletions(-)
 copy {drivers/pwm => include/linux/platform_data/x86}/pwm-lpss.h (51%)


base-commit: 3886bc3523db24814c98c57d74fe66d7a21bf40b

Comments

Linus Walleij Nov. 9, 2022, 9:01 a.m. UTC | #1 
On Tue, Nov 8, 2022 at 3:22 PM Andy Shevchenko
<andriy.shevchenko@linux.intel.com> wrote:

> I would like to route this via Intel pin control tree with issuing
> an immutable branch for both PINCTRL and PWM subsystems, but I'm
> open for other suggestions.

I'm fine with this approach if it works for Uwe.

Yours,
Linus Walleij
Thierry Reding Nov. 9, 2022, 5:40 p.m. UTC | #2 
On Tue, Nov 08, 2022 at 04:22:20PM +0200, Andy Shevchenko wrote:
> This is a continuation of the previously applied PWM LPSS cleanup series.
> Now, we would like to enable PWM optional feature that may be embedded
> into Intel pin control IPs (starting from Sky Lake platforms).
> 
> I would like to route this via Intel pin control tree with issuing
> an immutable branch for both PINCTRL and PWM subsystems, but I'm
> open for other suggestions.

I don't have any objections for this to go through the Intel tree as
long as Uwe is happy with this. Most of this is just reworking existing
things and the stub additions look good to me, so:

Acked-by: Thierry Reding <thierry.reding@gmail.com>
Andy Shevchenko Nov. 9, 2022, 5:49 p.m. UTC | #3 
On Wed, Nov 09, 2022 at 06:40:02PM +0100, Thierry Reding wrote:
> On Tue, Nov 08, 2022 at 04:22:20PM +0200, Andy Shevchenko wrote:
> > This is a continuation of the previously applied PWM LPSS cleanup series.
> > Now, we would like to enable PWM optional feature that may be embedded
> > into Intel pin control IPs (starting from Sky Lake platforms).
> > 
> > I would like to route this via Intel pin control tree with issuing
> > an immutable branch for both PINCTRL and PWM subsystems, but I'm
> > open for other suggestions.
> 
> I don't have any objections for this to go through the Intel tree as
> long as Uwe is happy with this.

So far Uwe acknowledged patch 2 only, hopefully he will have time to go
thru the rest.

> Most of this is just reworking existing
> things and the stub additions look good to me, so:
> 
> Acked-by: Thierry Reding <thierry.reding@gmail.com>

Thank you!