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d="scan'208";a="809762537" Received: from araj-dh-work.jf.intel.com ([10.165.157.158]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2022 10:59:17 -0700 From: Ashok Raj To: Borislav Petkov , Thomas Gleixner Cc: "LKML Mailing List" , X86-kernel , Tony Luck , Dave Hansen , Arjan van de Ven , Andy Lutomirski , Jacon Jun Pan , Tom Lendacky , Kai Huang , Andrew Cooper , Ashok Raj Subject: [v2 00/13] Make microcode late loading more robust Date: Thu, 3 Nov 2022 17:58:48 +0000 Message-Id: <20221103175901.164783-1-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-5.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748498878328826840?= X-GMAIL-MSGID: =?utf-8?q?1748498878328826840?= Hi Thomas & Boris This series is based on the recent cleanup series from Boris, here below: https://lore.kernel.org/lkml/20221028142638.28498-1-bp@alien8.de/ Previous post here: https://lore.kernel.org/lkml/20221014200913.14644-1-ashok.raj@intel.com/ Ashok Raj (12): x86/microcode/intel: Prevent printing updated microcode rev multiple times x86/microcode/intel: Print old and new rev after early microcode update x86/microcode/intel: Fix a hang if early loading microcode fails x86/microcode: Fix microcode_check() compare after a new uCode update x86/microcode: Move late-load warning to earlier where kernel taint happens x86/microcode: Place siblings in NMI loop while update in progress x86/mce: Warn of a microcode update is in progress when MCE arrives x86/microcode/intel: Add minimum required revision to microcode header x86/microcode: Add a generic mechanism to declare support for minrev x86/microcode/intel: Drop wbinvd() from microcode loading x86/microcode: Display revisions only when update is successful x86/microcode/intel: Add ability to update microcode even if rev is unchanged Jacob Pan (1): x86/ipi: Support sending NMI_VECTOR as self ipi arch/x86/include/asm/microcode.h | 43 ++++++ arch/x86/include/asm/microcode_intel.h | 4 +- arch/x86/include/asm/processor.h | 1 - arch/x86/kernel/apic/ipi.c | 6 +- arch/x86/kernel/apic/x2apic_phys.c | 6 +- arch/x86/kernel/cpu/common.c | 32 ---- arch/x86/kernel/cpu/mce/core.c | 5 + arch/x86/kernel/cpu/microcode/amd.c | 2 +- arch/x86/kernel/cpu/microcode/core.c | 200 +++++++++++++++++++++++-- arch/x86/kernel/cpu/microcode/intel.c | 96 ++++++++---- arch/x86/kernel/cpu/microcode/nmi.c | 71 +++++++++ arch/x86/kernel/nmi.c | 7 + arch/x86/kernel/nmi_selftest.c | 32 ++++ arch/x86/Kconfig | 7 +- arch/x86/kernel/cpu/microcode/Makefile | 1 + 15 files changed, 427 insertions(+), 86 deletions(-) create mode 100644 arch/x86/kernel/cpu/microcode/nmi.c